standalone : Modified code for MISRA-C:2012 compliance.
This patch unifies standalone for both Zynq and ZynqMP platforms. Also follows misrac guidelines. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This commit is contained in:
parent
9e1c9c1b60
commit
3f6f63b07e
267 changed files with 21724 additions and 5161 deletions
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@ -1,34 +1,45 @@
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###############################################################################
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##############################################################################
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#
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# Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
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# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
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#
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||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
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||||
# in the Software without restriction, including without limitation the rights
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||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
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||||
# This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
# and is protected under U.S. and international copyright and other
|
||||
# intellectual property laws.
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
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||||
# all copies or substantial portions of the Software.
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any rights to the
|
||||
# materials distributed herewith. Except as otherwise provided in a valid
|
||||
# license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
# applicable law:
|
||||
# (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
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||||
# XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
# OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
# NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
|
||||
# and
|
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# (2) Xilinx shall not be liable (whether in contract or tort, including
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# negligence, or under any other theory of liability) for any loss or damage of
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# any kind or nature related to, arising under or in connection with these
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# materials, including for any direct, or any indirect, special, incidental,
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# or consequential loss or damage (including loss of data, profits, goodwill,
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# or any type of loss or damage suffered as a result of any action brought
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# by a third party) even if such damage or loss was reasonably foreseeable
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# or Xilinx had been advised of the possibility of the same.
|
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#
|
||||
# Use of the Software is limited solely to applications:
|
||||
# (a) running on a Xilinx device, or
|
||||
# (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
# any application requiring fail-safe performance, such as life-support or
|
||||
# safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any other applications
|
||||
# that could lead to death, personal injury, or severe property or environmental
|
||||
# damage (individually and collectively, "Critical Applications").
|
||||
# Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
# Critical Applications, subject only to applicable laws and regulations
|
||||
# governing limitations on product liability.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
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# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
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# SOFTWARE.
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
# AT ALL TIMES.
|
||||
#
|
||||
# Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
# in advertising or otherwise to promote the sale, use or other dealings in
|
||||
# this Software without prior written authorization from Xilinx.
|
||||
#
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###############################################################################
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##############################################################################
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# ----------------------------------------------------------------------------
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# The following are hardcoded for Zynq.
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@ -64,9 +75,12 @@ proc generate {os_handle} {
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set enable_sw_profile [get_property CONFIG.enable_sw_intrusive_profiling $os_handle]
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set mb_exceptions false
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# proctype should be "microblaze" or ps7_cortexa9
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# proctype should be "microblaze" or pss_cortexa53 or pss_cortexr5 or ps7_cortexa9
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set mbsrcdir "./src/microblaze"
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set cortexa53srcdir "./src/cortexa53"
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set cortexr5srcdir "./src/cortexr5"
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set cortexa9srcdir "./src/cortexa9"
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set procdrv [get_sw_processor]
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set commonsrcdir "./src/common"
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foreach entry [glob -nocomplain [file join $commonsrcdir *]] {
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@ -76,7 +90,7 @@ proc generate {os_handle} {
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# Only processor specific file should be copied to specified standalone folder
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# write a API which needs compiler,
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switch $proctype {
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"microblaze" {
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"microblaze" {
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foreach entry [glob -nocomplain [file join $mbsrcdir *]] {
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# Copy over only files that are not related to exception handling. All such files have exception in their names
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file copy -force $entry "./src/"
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@ -84,6 +98,38 @@ proc generate {os_handle} {
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set need_config_file "true"
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set mb_exceptions [mb_has_exceptions $hw_proc_handle]
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}
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"pss_cortexa53" {
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set procdrv [get_sw_processor]
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set ccdir "./src/cortexa53/gcc"
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foreach entry [glob -nocomplain [file join $cortexa53srcdir *]] {
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file copy -force $entry "./src/"
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}
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foreach entry [glob -nocomplain [file join $ccdir *]] {
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file copy -force $entry "./src/"
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}
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file delete -force "./src/gcc"
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set file_handle [::hsm::utils::open_include_file "xparameters.h"]
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puts $file_handle "#include \"xparameters_ps.h\""
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puts $file_handle ""
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close $file_handle
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}
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"pss_cortexr5" {
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set procdrv [get_sw_processor]
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set ccdir "./src/cortexr5/gcc"
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foreach entry [glob -nocomplain [file join $cortexr5srcdir *]] {
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file copy -force $entry "./src/"
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}
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foreach entry [glob -nocomplain [file join $ccdir *]] {
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file copy -force $entry "./src/"
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}
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file delete -force "./src/gcc"
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set file_handle [::hsm::utils::open_include_file "xparameters.h"]
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puts $file_handle "#include \"xparameters_ps.h\""
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puts $file_handle ""
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close $file_handle
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}
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"ps7_cortexa9" {
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set procdrv [get_sw_processor]
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set compiler [get_property CONFIG.compiler $procdrv]
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@ -125,6 +171,10 @@ proc generate {os_handle} {
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if { $proctype == "microblaze" } {
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puts $makeconfig "LIBSOURCES = *.c *.S"
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puts $makeconfig "PROFILE_ARCH_OBJS = profile_mcount_mb.o"
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} elseif { $proctype == "pss_cortexr5" } {
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puts $makeconfig "LIBSOURCES = *.c *.S"
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} elseif { $proctype == "pss_cortexa53" } {
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puts $makeconfig "LIBSOURCES = *.c *.s *.S"
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} elseif { $proctype == "ps7_cortexa9" } {
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if {[string compare -nocase $compiler "armcc"] == 0} {
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puts $makeconfig "LIBSOURCES = *.c *.s"
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@ -144,8 +194,10 @@ proc generate {os_handle} {
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}
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close $makeconfig
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# Remove microblaze, cortexa9 and common directories...
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# Remove microblaze, cortexr5, cortexa53 and common directories...
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file delete -force $mbsrcdir
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file delete -force $cortexr5srcdir
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file delete -force $cortexa53srcdir
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file delete -force $cortexa9srcdir
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file delete -force $commonsrcdir
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@ -528,7 +580,7 @@ proc handle_profile { os_handle proctype } {
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set proc [get_sw_processor]
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if {$proctype == "ps7_cortexa9"} {
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if {{$proctype == "pss_cortexa53"} | {$proctype == "pss_cortexr5"} | {$proctype == "ps7_cortexa9"}} {
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set sw_proc_handle [get_sw_processor]
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set hw_proc_handle [get_cells [get_property HW_INSTANCE $sw_proc_handle]]
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set cpu_freq [get_property CONFIG.C_CPU_CLK_FREQ_HZ $hw_proc_handle]
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@ -557,7 +609,7 @@ proc handle_profile { os_handle proctype } {
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puts $config_file "#define SAMPLE_FREQ_HZ 100000"
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puts $config_file "#define TIMER_CLK_TICKS [expr $cpu_freq / 100000]"
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# proctype should be "microblaze" or "ps7_cortexa9"
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# proctype should be "microblaze" or "pss_cortexa53"
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switch $proctype {
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"microblaze" {
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# Microblaze Processor.
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@ -571,6 +623,37 @@ proc handle_profile { os_handle proctype } {
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}
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}
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"pss_cortexa53" {
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# Cortex A53 Processor.
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puts $config_file "#define PROC_CORTEXA53 1"
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set timer_inst [get_property CONFIG.profile_timer $os_handle]
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if { [string compare -nocase $timer_inst "none"] == 0 } {
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# SCU Timer
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puts $config_file "#define ENABLE_SCU_TIMER 1"
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puts $config_file "#define ENABLE_SYS_INTR 1"
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puts $config_file "#define PROFILE_TIMER_BASEADDR $scutimer_baseaddr"
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puts $config_file "#define PROFILE_TIMER_INTR_ID $scutimer_intr"
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puts $config_file "#define SCUGIC_CPU_BASEADDR $scugic_cpu_base"
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puts $config_file "#define SCUGIC_DIST_BASEADDR $scugic_dist_base"
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}
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}
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"pss_cortexr5" {
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# Cortex R5 Processor.
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puts $config_file "#define PROC_CORTEXR5 1"
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set timer_inst [get_property CONFIG.profile_timer $os_handle]
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if { [string compare -nocase $timer_inst "none"] == 0 } {
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# SCU Timer
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puts $config_file "#define ENABLE_SCU_TIMER 1"
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puts $config_file "#define ENABLE_SYS_INTR 1"
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puts $config_file "#define PROFILE_TIMER_BASEADDR $scutimer_baseaddr"
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puts $config_file "#define PROFILE_TIMER_INTR_ID $scutimer_intr"
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puts $config_file "#define SCUGIC_CPU_BASEADDR $scugic_cpu_base"
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puts $config_file "#define SCUGIC_DIST_BASEADDR $scugic_dist_base"
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}
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}
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"ps7_cortexa9" {
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# Cortex A9 Processor.
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@ -3,210 +3,5 @@
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
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* 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
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* 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
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* cacheable regions
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* Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
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* generated by the cpu driver, for enabling caches
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* 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
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* write-thru caches
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* 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
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* Updated the MMU table to mark OCM in high address space
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* as inner cacheable and reserved space as Invalid
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* 3.03a sdm 08/20/11 Changes to support FreeRTOS
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* Updated the MMU table to mark upper half of the DDR as
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* non-cacheable
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* Setup supervisor and abort mode stacks
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* Do not initialize/enable L2CC in case of AMP
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* Initialize UART1 for 9600bps in case of AMP
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* 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
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* in case of AMP
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* 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
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* counters
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* 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
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* xparameters.h file for CR630532 - Xil_DCacheFlush()/
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* Xil_DCacheFlushRange() functions in standalone BSP v3_02a
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* for MicroBlaze will invalidate data in the cache instead
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* of flushing it for writeback caches
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* 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
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* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
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* Remove redundant dsb/dmb instructions in cache maintenance
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* APIs
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* Remove redundant dsb in mcr instruction
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* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
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* 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
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* driver tcl in xparameters.h. Update the gcc/translationtable.s
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* for the QSPI complete address range - DT644567
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* Removed profile directory for armcc compiler and changed
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* profiling setting to false in standalone_v2_1_0.tcl file
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* Deleting boot.S file after preprocessing for armcc compiler
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* 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
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* invalidate the caches before enabling back the MMU and
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* D cache.
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* 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
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* xil_mmu.c. Now we invalidate UTLB, Branch predictor
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* array, flush the D-cache before changing the attributes
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* in translation table. The user need not call Xil_DisableMMU
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* before calling Xil_SetTlbAttributes.
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* 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
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* sgd initialization is present. Changes for this were done in
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* uart.c and xil-crt0.s.
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* Made changes in xil_io.c to use volatile pointers.
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* Made changes in xil_mmu.c to correct the function
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* Xil_SetTlbAttributes.
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* Changes are made xil-crt0.s to initialize the static
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* C++ constructors.
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* Changes are made in boot.s, to fix the TTBR settings,
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* correct the L2 Cache Auxiliary register settings, L2 cache
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* latency settings.
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* 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
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* sgd usleep.c to use global timer intstead of CP15.
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* Made changes in cortexa9/gcc/translation_table.s to map
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* the peripheral devices as shareable device memory.
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* Made changes in cortexa9/gcc/xil-crt0.s to initialize
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* the global timer.
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* Made changes in cortexa9/armcc/boot.S to initialize
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* the global timer.
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* Made changes in cortexa9/armcc/translation_table.s to
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* map the peripheral devices as shareable device memory.
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* Made changes in cortexa9/gcc/boot.S to optimize the
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* L2 cache settings. Changes the section properties for
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* ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
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* and cortexa9/gcc/translation_table.S.
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* Made changes in cortexa9/xil_cache.c to change the
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* cache invalidation order.
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* 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
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* compilation/linking issues for C++ compiler.
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* Made changes in mb_interface.h to remove compilation/
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* linking issues for C++ compiler.
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* Added macros for swapb and swaph microblaze instructions
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* mb_interface.h
|
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* Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
|
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* for CortexA9.
|
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* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
|
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* 3.07a asa 08/31/12 Added xil_printf.h include
|
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* 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
|
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* Corrected L2 cache sequence disable sequence
|
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* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
|
||||
* 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
|
||||
* irq/fiq handling.
|
||||
* Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
|
||||
* fixes the CR #692094.
|
||||
* 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
|
||||
* 3.10a srt 04/18/13 Implemented ARM Erratas.
|
||||
* Cortex A9 Errata - 742230, 743622, 775420, 794073
|
||||
* L2Cache PL310 Errata - 588369, 727915, 759370
|
||||
* Please refer to file 'xil_errata.h' for errata
|
||||
* description.
|
||||
* 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
|
||||
* cache APIs were corresponding to only Layer 1 cache
|
||||
* memories. New APIs were now added and the existing cache
|
||||
* related APIs were changed to provide a uniform interface
|
||||
* to flush/invalidate/enable/disable the complete cache
|
||||
* system which includes both L1 and L2 caches. The changes
|
||||
* for these were done in:
|
||||
* src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
|
||||
* files.
|
||||
* Four new files were added for supporting L2 cache. They are:
|
||||
* microblaze_flush_cache_ext.S-> Flushes L2 cache
|
||||
* microblaze_flush_cache_ext_range.S -> Flushes a range of
|
||||
* memory in L2 cache.
|
||||
* microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
|
||||
* microblaze_invalidate_cache_ext_range -> Invalidates a
|
||||
* range of memory in L2 cache.
|
||||
* These changes are done to implement PR #697214.
|
||||
* 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
|
||||
* fix the CR #706464. L2 cache disabling happens independent
|
||||
* of L1 data cache disable operation. Changes are done in the
|
||||
* same file in cache handling APIs to do a L2 cache sync
|
||||
* (poll reg7_?cache_?sync). This fixes CR #700542.
|
||||
* 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
|
||||
* interrupts for ARM. These are done to fix the CR#699680.
|
||||
* 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
|
||||
* sync operation. This fixes the CR# 716781.
|
||||
* 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
|
||||
* for armcc toolchain.
|
||||
* Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
|
||||
* fix issues related to NEON context saving. The assembly
|
||||
* routines for IRQ and FIQ handling are modified.
|
||||
* Deprecated the older BSP (3.10a).
|
||||
* 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
|
||||
* various potential issues. Made changes in the function
|
||||
* Xil_SetAttributes in file xil_mmu.c.
|
||||
* 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
|
||||
* in src\cortexa9 and src\microblaze folders.
|
||||
* 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
|
||||
* L2 cache sync operation and to fix issues around complete
|
||||
* L2 cache flush/invalidation by ways.
|
||||
* 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
|
||||
* to fix linking issues with armcc/DS-5. Modified the armcc
|
||||
* makefile to fix issues.
|
||||
* 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
|
||||
* 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
|
||||
* 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
|
||||
* and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
|
||||
* src\cortexa9\armcc\) to fix CR#767251
|
||||
* 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
|
||||
* Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
|
||||
* Few cache lines were missed to invalidate when unaligned address
|
||||
* invalidation was accommodated in Xil_DCacheInvalidateRange.
|
||||
* In Xil_L1DCacheInvalidate, while invalidating all L1D cache
|
||||
* stack memory (which contains return address) was invalidated. So
|
||||
* stack memory is flushed first and then L1D cache is invalidated.
|
||||
* This is done to fix CR #763829
|
||||
* 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
|
||||
* mblaze_nt_types.h file and replace uint32_t with u32 in the
|
||||
* profile_hist.c to fix the above CR.
|
||||
* 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
|
||||
* instead of libxil.a and added prototypes for
|
||||
* microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
|
||||
* mb_interface.h
|
||||
* 4.1 hk 04/18/14 Add sleep function.
|
||||
* 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
|
||||
* some of the *.s files inMB BSP source to *.S.
|
||||
* 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
|
||||
* 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
|
||||
* CR#794205
|
||||
* 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
|
||||
* common/xil_testcache.c
|
||||
* Fix for CR#764881.
|
||||
* 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
|
||||
* output the DEBUG logs when -DDEBUG flag is enabled in BSP.
|
||||
* 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
|
||||
* Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
|
||||
* 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
|
||||
* cortexa9/armcc/boot.s. Added default exception handlers for data
|
||||
* abort and prefetch abort using handlers called
|
||||
* DataAbortHandler and PrefetchAbortHandler respectively in
|
||||
* cortexa9/xil_exception.c to fix CR#802862.
|
||||
* 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
|
||||
* issue of improper linking of translation_table.s
|
||||
* 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
|
||||
* in tool chain to avoid conflicts into some special cases
|
||||
* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
|
||||
* Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
|
||||
* 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
|
||||
* containing type def u32 defined in xil_types.g to resolve issue of
|
||||
* CR#805869
|
||||
* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
|
||||
* it is not possible to generate timer in nanosecond due to limited
|
||||
* cpu frequency
|
||||
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
|
||||
* uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
|
||||
* and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
|
||||
* removed function definition of XSmc_NorInit and XSmc_NorInit from
|
||||
* cortexa9/smc.h
|
||||
* 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
|
||||
* cache_ext_range declarations in mb_interface.h CR#783821.
|
||||
* Modified profile_mcount_mb.S to fix CR#808412.
|
||||
* 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
|
||||
* cortexa9/iccarm to fix CR#816701
|
||||
* 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
|
||||
* armcc/translation_table.s and iccarm/translation_table.s
|
||||
* to properly defined reserved entries according to address map for
|
||||
* fixing CR#820146
|
||||
* 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
|
||||
* and cortexa9/armcc/translation_table.s to resolve compilation
|
||||
* error for solving CR#822897
|
||||
******************************************************************************************/
|
||||
* 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.
|
||||
*****************************************************************************************/
|
||||
|
|
63
lib/bsp/standalone/src/common/xbasic_types.h
Executable file → Normal file
63
lib/bsp/standalone/src/common/xbasic_types.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -89,15 +100,15 @@ typedef Xuint8 u8;
|
|||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
# define TRUE 1
|
||||
# define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
# define FALSE 0
|
||||
# define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
4
lib/bsp/standalone/src/common/xdebug.h
Executable file → Normal file
4
lib/bsp/standalone/src/common/xdebug.h
Executable file → Normal file
|
@ -1,6 +1,8 @@
|
|||
#ifndef XDEBUG
|
||||
#define XDEBUG
|
||||
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#if defined(DEBUG) && !defined(NDEBUG)
|
||||
|
||||
#ifndef XDEBUG_WARNING
|
||||
|
|
57
lib/bsp/standalone/src/common/xenv.h
Executable file → Normal file
57
lib/bsp/standalone/src/common/xenv.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
|
75
lib/bsp/standalone/src/common/xenv_standalone.h
Executable file → Normal file
75
lib/bsp/standalone/src/common/xenv_standalone.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -66,6 +77,8 @@
|
|||
#ifndef XENV_STANDALONE_H
|
||||
#define XENV_STANDALONE_H
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
@ -149,7 +162,7 @@ extern "C" {
|
|||
*****************************************************************************/
|
||||
|
||||
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
|
||||
memset((void *) DestPtr, (int) Data, (size_t) Bytes)
|
||||
memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
|
||||
|
||||
|
||||
|
||||
|
@ -163,7 +176,7 @@ extern "C" {
|
|||
* A structure that contains a time stamp used by other time stamp macros
|
||||
* defined below. This structure is processor dependent.
|
||||
*/
|
||||
typedef int XENV_TIME_STAMP;
|
||||
typedef s32 XENV_TIME_STAMP;
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
|
@ -278,16 +291,16 @@ typedef int XENV_TIME_STAMP;
|
|||
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
|
||||
|
||||
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
|
||||
microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
|
||||
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
|
||||
|
||||
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
|
||||
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
|
||||
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
|
||||
microblaze_flush_dcache_range((int)(Addr), (int)(Len))
|
||||
microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
|
||||
#else
|
||||
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
|
||||
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
|
||||
microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
|
||||
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
|
||||
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
|
||||
|
||||
#else
|
||||
|
@ -307,7 +320,7 @@ typedef int XENV_TIME_STAMP;
|
|||
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
|
||||
|
||||
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
|
||||
microblaze_invalidate_icache_range((int)(Addr), (int)(Len))
|
||||
microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
|
||||
|
||||
#else
|
||||
# define XCACHE_ENABLE_ICACHE()
|
||||
|
@ -340,10 +353,10 @@ typedef int XENV_TIME_STAMP;
|
|||
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
|
||||
|
||||
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
|
||||
XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len))
|
||||
XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
|
||||
|
||||
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
|
||||
XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len))
|
||||
XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
|
||||
|
||||
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
|
||||
|
||||
|
|
68
lib/bsp/standalone/src/common/xil_assert.c
Executable file → Normal file
68
lib/bsp/standalone/src/common/xil_assert.c
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -64,14 +75,14 @@
|
|||
* sets this variable such that a driver can evaluate this variable
|
||||
* to determine if an assert occurred.
|
||||
*/
|
||||
unsigned int Xil_AssertStatus;
|
||||
u32 Xil_AssertStatus;
|
||||
|
||||
/**
|
||||
* This variable allows the assert functionality to be changed for testing
|
||||
* such that it does not wait infinitely. Use the debugger to disable the
|
||||
* waiting during testing of asserts.
|
||||
*/
|
||||
int Xil_AssertWait = TRUE;
|
||||
/*s32 Xil_AssertWait = 1*/
|
||||
|
||||
/* The callback function to be invoked when an assert is taken */
|
||||
static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
|
||||
|
@ -93,8 +104,9 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
|
|||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Assert(const char *File, int Line)
|
||||
void Xil_Assert(const char8 *File, s32 Line)
|
||||
{
|
||||
s32 Xil_AssertWait = 1;
|
||||
/* if the callback has been set then invoke it */
|
||||
if (Xil_AssertCallbackRoutine != 0) {
|
||||
(*Xil_AssertCallbackRoutine)(File, Line);
|
||||
|
@ -103,7 +115,7 @@ void Xil_Assert(const char *File, int Line)
|
|||
/* if specified, wait indefinitely such that the assert will show up
|
||||
* in testing
|
||||
*/
|
||||
while (Xil_AssertWait) {
|
||||
while (Xil_AssertWait != 0) {
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -141,6 +153,6 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine)
|
|||
******************************************************************************/
|
||||
void XNullHandler(void *NullParameter)
|
||||
{
|
||||
(void) NullParameter;
|
||||
(void *) NullParameter;
|
||||
}
|
||||
|
||||
|
|
71
lib/bsp/standalone/src/common/xil_assert.h
Executable file → Normal file
71
lib/bsp/standalone/src/common/xil_assert.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -59,19 +70,19 @@ extern "C" {
|
|||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#define XIL_ASSERT_NONE 0
|
||||
#define XIL_ASSERT_OCCURRED 1
|
||||
#define XIL_ASSERT_NONE 0U
|
||||
#define XIL_ASSERT_OCCURRED 1U
|
||||
#define XNULL NULL
|
||||
|
||||
extern unsigned int Xil_AssertStatus;
|
||||
extern void Xil_Assert(const char *, int);
|
||||
extern u32 Xil_AssertStatus;
|
||||
extern void Xil_Assert(const char8 *File, s32 Line);
|
||||
void XNullHandler(void *NullParameter);
|
||||
|
||||
/**
|
||||
* This data type defines a callback to be invoked when an
|
||||
* assert occurs. The callback is invoked only when asserts are enabled
|
||||
*/
|
||||
typedef void (*Xil_AssertCallback) (const char *File, int Line);
|
||||
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
|
@ -83,7 +94,7 @@ typedef void (*Xil_AssertCallback) (const char *File, int Line);
|
|||
* (void). This in conjunction with the Xil_AssertWait boolean can be used to
|
||||
* accomodate tests so that asserts which fail allow execution to continue.
|
||||
*
|
||||
* @param expression is the expression to evaluate. If it evaluates to
|
||||
* @param Expression is the expression to evaluate. If it evaluates to
|
||||
* false, the assert occurs.
|
||||
*
|
||||
* @return Returns void unless the Xil_AssertWait variable is true, in which
|
||||
|
@ -109,7 +120,7 @@ typedef void (*Xil_AssertCallback) (const char *File, int Line);
|
|||
* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
|
||||
* so that asserts which fail allow execution to continue.
|
||||
*
|
||||
* @param expression is the expression to evaluate. If it evaluates to false,
|
||||
* @param Expression is the expression to evaluate. If it evaluates to false,
|
||||
* the assert occurs.
|
||||
*
|
||||
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
|
||||
|
|
57
lib/bsp/standalone/src/common/xil_cache_vxworks.h
Executable file → Normal file
57
lib/bsp/standalone/src/common/xil_cache_vxworks.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
|
57
lib/bsp/standalone/src/common/xil_hal.h
Executable file → Normal file
57
lib/bsp/standalone/src/common/xil_hal.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
|
57
lib/bsp/standalone/src/common/xil_macroback.h
Executable file → Normal file
57
lib/bsp/standalone/src/common/xil_macroback.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
|
271
lib/bsp/standalone/src/common/xil_testcache.c
Executable file → Normal file
271
lib/bsp/standalone/src/common/xil_testcache.c
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -51,19 +62,25 @@
|
|||
* This file contain functions that all operate on HAL.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifdef __ARM__
|
||||
#include "xil_cache.h"
|
||||
#include "xil_testcache.h"
|
||||
#include "xil_types.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#ifdef __aarch64__
|
||||
#include "xreg_cortexa53.h"
|
||||
#else
|
||||
#include "xreg_cortexr5.h"
|
||||
#endif
|
||||
|
||||
extern void xil_printf(const char *ctrl1, ...);
|
||||
extern void xil_printf(const char8 *ctrl1, ...);
|
||||
|
||||
#define DATA_LENGTH 128
|
||||
|
||||
#ifdef __GNUC__
|
||||
static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32)));
|
||||
#elif defined (__ICCARM__)
|
||||
static u32 Data[DATA_LENGTH];
|
||||
#ifdef __aarch64__
|
||||
static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
|
||||
#else
|
||||
static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32)));
|
||||
static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -77,30 +94,35 @@ static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32)));
|
|||
* - 0 is returned for a pass
|
||||
* - -1 is returned for a failure
|
||||
*/
|
||||
int Xil_TestDCacheRange(void)
|
||||
s32 Xil_TestDCacheRange(void)
|
||||
{
|
||||
int Index;
|
||||
int Status;
|
||||
|
||||
u32 Value;
|
||||
s32 Index;
|
||||
s32 Status = 0;
|
||||
u32 CtrlReg;
|
||||
INTPTR Value;
|
||||
|
||||
xil_printf("-- Cache Range Test --\n\r");
|
||||
|
||||
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++)
|
||||
Data[Index] = 0xA0A00505;
|
||||
|
||||
xil_printf(" initialize Data done:\r\n");
|
||||
|
||||
Xil_DCacheFlushRange((u32)Data, DATA_LENGTH * sizeof(u32));
|
||||
Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
|
||||
|
||||
xil_printf(" flush range done\r\n");
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++)
|
||||
Data[Index] = Index + 3;
|
||||
|
||||
Xil_DCacheInvalidateRange((u32)Data, DATA_LENGTH * sizeof(u32));
|
||||
|
||||
xil_printf(" invalidate dcache range done\r\n");
|
||||
dsb();
|
||||
#ifdef __aarch64__
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
#else
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
|
||||
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#endif
|
||||
dsb();
|
||||
|
||||
Status = 0;
|
||||
|
||||
|
@ -113,15 +135,80 @@ int Xil_TestDCacheRange(void)
|
|||
}
|
||||
}
|
||||
|
||||
if (!Status) {
|
||||
xil_printf(" Flush worked\r\n");
|
||||
}
|
||||
else {
|
||||
xil_printf("Error: flush dcache range not working\r\n");
|
||||
}
|
||||
dsb();
|
||||
#ifdef __aarch64__
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
#else
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
|
||||
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#endif
|
||||
dsb();
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++)
|
||||
Data[Index] = 0xA0A0C505;
|
||||
|
||||
|
||||
|
||||
Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
|
||||
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++)
|
||||
Data[Index] = Index + 3;
|
||||
|
||||
Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
|
||||
|
||||
xil_printf(" invalidate dcache range done\r\n");
|
||||
dsb();
|
||||
#ifdef __aarch64__
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
#else
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
|
||||
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#endif
|
||||
dsb();
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++)
|
||||
Data[Index] = 0xA0A0A05;
|
||||
dsb();
|
||||
#ifdef __aarch64__
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
#else
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
|
||||
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#endif
|
||||
dsb();
|
||||
|
||||
Status = 0;
|
||||
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++) {
|
||||
Value = Data[Index];
|
||||
if (Value != 0xA0A0A05) {
|
||||
Status = -1;
|
||||
xil_printf("Data[%d] = %x\r\n", Index, Value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (!Status) {
|
||||
xil_printf(" Invalidate worked\r\n");
|
||||
}
|
||||
else {
|
||||
xil_printf("Error: Invalidate dcache range not working\r\n");
|
||||
}
|
||||
|
||||
xil_printf("-- Cache Range Test Complete --\r\n");
|
||||
|
||||
return Status;
|
||||
|
||||
}
|
||||
|
@ -136,23 +223,66 @@ int Xil_TestDCacheRange(void)
|
|||
* - 0 is returned for a pass
|
||||
* - -1 is returned for a failure
|
||||
*/
|
||||
int Xil_TestDCacheAll(void)
|
||||
s32 Xil_TestDCacheAll(void)
|
||||
{
|
||||
int Index;
|
||||
int Status;
|
||||
u32 Value;
|
||||
s32 Index;
|
||||
s32 Status;
|
||||
INTPTR Value;
|
||||
u32 CtrlReg;
|
||||
|
||||
xil_printf("-- Cache All Test --\n\r");
|
||||
|
||||
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++)
|
||||
Data[Index] = 0x50500A0A;
|
||||
|
||||
xil_printf(" initialize Data done:\r\n");
|
||||
|
||||
Xil_DCacheFlush();
|
||||
|
||||
xil_printf(" flush all done\r\n");
|
||||
dsb();
|
||||
#ifdef __aarch64__
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
#else
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
|
||||
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#endif
|
||||
dsb();
|
||||
Status = 0;
|
||||
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++) {
|
||||
Value = Data[Index];
|
||||
|
||||
if (Value != 0x50500A0A) {
|
||||
Status = -1;
|
||||
xil_printf("Data[%d] = %x\r\n", Index, Value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!Status) {
|
||||
xil_printf(" Flush all worked\r\n");
|
||||
}
|
||||
else {
|
||||
xil_printf("Error: Flush dcache all not working\r\n");
|
||||
}
|
||||
dsb();
|
||||
#ifdef __aarch64__
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
#else
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
|
||||
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#endif
|
||||
dsb();
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++)
|
||||
Data[Index] = 0x505FFA0A;
|
||||
|
||||
Xil_DCacheFlush();
|
||||
|
||||
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++)
|
||||
Data[Index] = Index + 3;
|
||||
|
@ -160,12 +290,35 @@ int Xil_TestDCacheAll(void)
|
|||
Xil_DCacheInvalidate();
|
||||
|
||||
xil_printf(" invalidate all done\r\n");
|
||||
|
||||
dsb();
|
||||
#ifdef __aarch64__
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
#else
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
|
||||
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#endif
|
||||
dsb();
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++)
|
||||
Data[Index] = 0x50CFA0A;
|
||||
dsb();
|
||||
#ifdef __aarch64__
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
#else
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
|
||||
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#endif
|
||||
dsb();
|
||||
Status = 0;
|
||||
|
||||
for (Index = 0; Index < DATA_LENGTH; Index++) {
|
||||
Value = Data[Index];
|
||||
if (Value != 0x50500A0A) {
|
||||
if (Value != 0x50CFA0A) {
|
||||
Status = -1;
|
||||
xil_printf("Data[%d] = %x\r\n", Index, Value);
|
||||
break;
|
||||
|
@ -176,13 +329,12 @@ int Xil_TestDCacheAll(void)
|
|||
xil_printf(" Invalidate all worked\r\n");
|
||||
}
|
||||
else {
|
||||
xil_printf("Error: Invalidate dcache all not working\r\n");
|
||||
xil_printf("Error: Invalidate dcache all not working\r\n");
|
||||
}
|
||||
|
||||
xil_printf("-- DCache all Test Complete --\n\r");
|
||||
|
||||
return Status;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
@ -194,12 +346,12 @@ int Xil_TestDCacheAll(void)
|
|||
* - 0 is returned for a pass
|
||||
* The function will hang if it fails.
|
||||
*/
|
||||
int Xil_TestICacheRange(void)
|
||||
s32 Xil_TestICacheRange(void)
|
||||
{
|
||||
|
||||
Xil_ICacheInvalidateRange((u32)Xil_TestICacheRange, 1024);
|
||||
Xil_ICacheInvalidateRange((u32)Xil_TestDCacheRange, 1024);
|
||||
Xil_ICacheInvalidateRange((u32)Xil_TestDCacheAll, 1024);
|
||||
Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
|
||||
Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
|
||||
Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
|
||||
|
||||
xil_printf("-- Invalidate icache range done --\r\n");
|
||||
|
||||
|
@ -214,9 +366,10 @@ int Xil_TestICacheRange(void)
|
|||
* - 0 is returned for a pass
|
||||
* The function will hang if it fails.
|
||||
*/
|
||||
int Xil_TestICacheAll(void)
|
||||
s32 Xil_TestICacheAll(void)
|
||||
{
|
||||
Xil_ICacheInvalidate();
|
||||
xil_printf("-- Invalidate icache all done --\r\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
65
lib/bsp/standalone/src/common/xil_testcache.h
Executable file → Normal file
65
lib/bsp/standalone/src/common/xil_testcache.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -49,10 +60,10 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern int Xil_TestDCacheRange(void);
|
||||
extern int Xil_TestDCacheAll(void);
|
||||
extern int Xil_TestICacheRange(void);
|
||||
extern int Xil_TestICacheAll(void);
|
||||
extern s32 Xil_TestDCacheRange(void);
|
||||
extern s32 Xil_TestDCacheAll(void);
|
||||
extern s32 Xil_TestICacheRange(void);
|
||||
extern s32 Xil_TestICacheAll(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
166
lib/bsp/standalone/src/common/xil_testio.c
Executable file → Normal file
166
lib/bsp/standalone/src/common/xil_testio.c
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -60,19 +71,19 @@
|
|||
*
|
||||
* Endian swap a 16-bit word.
|
||||
* @param Data is the 16-bit word to be swapped.
|
||||
* @return The endian swapped valud.
|
||||
* @return The endian swapped value.
|
||||
*
|
||||
*/
|
||||
static u16 Swap16(u16 Data)
|
||||
{
|
||||
return ((Data >> 8) & 0x00FF) | ((Data << 8) & 0xFF00);
|
||||
return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* Endian swap a 32-bit word.
|
||||
* @param Data is the 32-bit word to be swapped.
|
||||
* @return The endian swapped valud.
|
||||
* @return The endian swapped value.
|
||||
*
|
||||
*/
|
||||
static u32 Swap32(u32 Data)
|
||||
|
@ -83,13 +94,13 @@ static u32 Swap32(u32 Data)
|
|||
u16 Swap16Lo;
|
||||
u16 Swap16Hi;
|
||||
|
||||
Hi16 = (u16)((Data >> 16) & 0x0000FFFF);
|
||||
Lo16 = (u16)(Data & 0x0000FFFF);
|
||||
Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
|
||||
Lo16 = (u16)(Data & 0x0000FFFFU);
|
||||
|
||||
Swap16Lo = Swap16(Lo16);
|
||||
Swap16Hi = Swap16(Hi16);
|
||||
|
||||
return (((u32)(Swap16Lo)) << 16) | ((u32)Swap16Hi);
|
||||
return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
@ -100,7 +111,7 @@ static u32 Swap32(u32 Data)
|
|||
* values.
|
||||
*
|
||||
* @param Addr is a pointer to the region of memory to be tested.
|
||||
* @param Len is the length of the block.
|
||||
* @param Length is the Length of the block.
|
||||
* @param Value is the constant used for writting the memory.
|
||||
*
|
||||
* @return
|
||||
|
@ -110,22 +121,23 @@ static u32 Swap32(u32 Data)
|
|||
*
|
||||
*****************************************************************************/
|
||||
|
||||
int Xil_TestIO8(u8 *Addr, int Len, u8 Value)
|
||||
s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
|
||||
{
|
||||
u8 ValueIn;
|
||||
int Index;
|
||||
s32 Index;
|
||||
s32 Status = 0;
|
||||
|
||||
for (Index = 0; Index < Len; Index++) {
|
||||
Xil_Out8((u32)Addr, Value);
|
||||
for (Index = 0; Index < Length; Index++) {
|
||||
Xil_Out8((INTPTR)Addr, Value);
|
||||
|
||||
ValueIn = Xil_In8((u32)Addr);
|
||||
ValueIn = Xil_In8((INTPTR)Addr);
|
||||
|
||||
if (Value != ValueIn) {
|
||||
return -1;
|
||||
if ((Value != ValueIn) && (Status == 0)) {
|
||||
Status = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
return Status;
|
||||
|
||||
}
|
||||
|
||||
|
@ -142,7 +154,7 @@ int Xil_TestIO8(u8 *Addr, int Len, u8 Value)
|
|||
* read-in value before comparing is controlled by the 5th argument.
|
||||
*
|
||||
* @param Addr is a pointer to the region of memory to be tested.
|
||||
* @param Len is the length of the block.
|
||||
* @param Length is the Length of the block.
|
||||
* @param Value is the constant used for writting the memory.
|
||||
* @param Kind is the test kind. Acceptable values are:
|
||||
* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
|
||||
|
@ -155,60 +167,63 @@ int Xil_TestIO8(u8 *Addr, int Len, u8 Value)
|
|||
*
|
||||
*****************************************************************************/
|
||||
|
||||
int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap)
|
||||
s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
|
||||
{
|
||||
u16 ValueIn;
|
||||
int Index;
|
||||
u16 *TempAddr16;
|
||||
u16 ValueIn = 0U;
|
||||
s32 Index;
|
||||
TempAddr16 = Addr;
|
||||
Xil_AssertNonvoid(TempAddr16 != NULL);
|
||||
|
||||
for (Index = 0; Index < Len; Index++) {
|
||||
for (Index = 0; Index < Length; Index++) {
|
||||
switch (Kind) {
|
||||
case XIL_TESTIO_LE:
|
||||
Xil_Out16LE((u32)Addr, Value);
|
||||
Xil_Out16LE((INTPTR)TempAddr16, Value);
|
||||
break;
|
||||
case XIL_TESTIO_BE:
|
||||
Xil_Out16BE((u32)Addr, Value);
|
||||
Xil_Out16BE((INTPTR)TempAddr16, Value);
|
||||
break;
|
||||
default:
|
||||
Xil_Out16((u32)Addr, Value);
|
||||
Xil_Out16((INTPTR)TempAddr16, Value);
|
||||
break;
|
||||
}
|
||||
|
||||
ValueIn = Xil_In16((u32)Addr);
|
||||
ValueIn = Xil_In16((INTPTR)TempAddr16);
|
||||
|
||||
if (Kind && Swap)
|
||||
if ((Kind != 0) && (Swap != 0)) {
|
||||
ValueIn = Swap16(ValueIn);
|
||||
}
|
||||
|
||||
if (Value != ValueIn) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* second round */
|
||||
Xil_Out16((u32)Addr, Value);
|
||||
Xil_Out16((INTPTR)TempAddr16, Value);
|
||||
|
||||
switch (Kind) {
|
||||
case XIL_TESTIO_LE:
|
||||
ValueIn = Xil_In16LE((u32)Addr);
|
||||
ValueIn = Xil_In16LE((INTPTR)TempAddr16);
|
||||
break;
|
||||
case XIL_TESTIO_BE:
|
||||
ValueIn = Xil_In16BE((u32)Addr);
|
||||
ValueIn = Xil_In16BE((INTPTR)TempAddr16);
|
||||
break;
|
||||
default:
|
||||
ValueIn = Xil_In16((u32)Addr);
|
||||
ValueIn = Xil_In16((INTPTR)TempAddr16);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
if (Kind && Swap)
|
||||
if ((Kind != 0) && (Swap != 0)) {
|
||||
ValueIn = Swap16(ValueIn);
|
||||
}
|
||||
|
||||
if (Value != ValueIn) {
|
||||
return -1;
|
||||
}
|
||||
Addr++;
|
||||
TempAddr16 += sizeof(u16);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
@ -225,7 +240,7 @@ int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap)
|
|||
* before comparing is controlled by the 5th argument.
|
||||
*
|
||||
* @param Addr is a pointer to the region of memory to be tested.
|
||||
* @param Len is the length of the block.
|
||||
* @param Length is the Length of the block.
|
||||
* @param Value is the constant used for writting the memory.
|
||||
* @param Kind is the test kind. Acceptable values are:
|
||||
* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
|
||||
|
@ -237,56 +252,61 @@ int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap)
|
|||
* - 0 is returned for a pass
|
||||
*
|
||||
*****************************************************************************/
|
||||
int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap)
|
||||
s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
|
||||
{
|
||||
u32 ValueIn;
|
||||
int Index;
|
||||
u32 *TempAddr;
|
||||
u32 ValueIn = 0U;
|
||||
s32 Index;
|
||||
TempAddr = Addr;
|
||||
Xil_AssertNonvoid(TempAddr != NULL);
|
||||
|
||||
for (Index = 0; Index < Len; Index++) {
|
||||
for (Index = 0; Index < Length; Index++) {
|
||||
switch (Kind) {
|
||||
case XIL_TESTIO_LE:
|
||||
Xil_Out32LE((u32)Addr, Value);
|
||||
Xil_Out32LE((INTPTR)TempAddr, Value);
|
||||
break;
|
||||
case XIL_TESTIO_BE:
|
||||
Xil_Out32BE((u32)Addr, Value);
|
||||
Xil_Out32BE((INTPTR)TempAddr, Value);
|
||||
break;
|
||||
default:
|
||||
Xil_Out32((u32)Addr, Value);
|
||||
Xil_Out32((INTPTR)TempAddr, Value);
|
||||
break;
|
||||
}
|
||||
|
||||
ValueIn = Xil_In32((u32)Addr);
|
||||
ValueIn = Xil_In32((INTPTR)TempAddr);
|
||||
|
||||
if (Kind && Swap)
|
||||
if ((Kind != 0) && (Swap != 0)) {
|
||||
ValueIn = Swap32(ValueIn);
|
||||
}
|
||||
|
||||
if (Value != ValueIn) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* second round */
|
||||
Xil_Out32((u32)Addr, Value);
|
||||
Xil_Out32((INTPTR)TempAddr, Value);
|
||||
|
||||
|
||||
switch (Kind) {
|
||||
case XIL_TESTIO_LE:
|
||||
ValueIn = Xil_In32LE((u32)Addr);
|
||||
ValueIn = Xil_In32LE((INTPTR)TempAddr);
|
||||
break;
|
||||
case XIL_TESTIO_BE:
|
||||
ValueIn = Xil_In32BE((u32)Addr);
|
||||
ValueIn = Xil_In32BE((INTPTR)TempAddr);
|
||||
break;
|
||||
default:
|
||||
ValueIn = Xil_In32((u32)Addr);
|
||||
ValueIn = Xil_In32((INTPTR)TempAddr);
|
||||
break;
|
||||
}
|
||||
|
||||
if (Kind && Swap)
|
||||
if ((Kind != 0) && (Swap != 0)) {
|
||||
ValueIn = Swap32(ValueIn);
|
||||
}
|
||||
|
||||
if (Value != ValueIn) {
|
||||
return -1;
|
||||
}
|
||||
Addr++;
|
||||
TempAddr += sizeof(u32);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
63
lib/bsp/standalone/src/common/xil_testio.h
Executable file → Normal file
63
lib/bsp/standalone/src/common/xil_testio.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -80,9 +91,9 @@ extern "C" {
|
|||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value);
|
||||
extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap);
|
||||
extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap);
|
||||
extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
|
||||
extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
|
||||
extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
602
lib/bsp/standalone/src/common/xil_testmem.c
Executable file → Normal file
602
lib/bsp/standalone/src/common/xil_testmem.c
Executable file → Normal file
File diff suppressed because it is too large
Load diff
77
lib/bsp/standalone/src/common/xil_testmem.h
Executable file → Normal file
77
lib/bsp/standalone/src/common/xil_testmem.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -127,7 +138,7 @@ extern "C" {
|
|||
|
||||
/* xutil_memtest defines */
|
||||
|
||||
#define XIL_TESTMEM_INIT_VALUE 1
|
||||
#define XIL_TESTMEM_INIT_VALUE 1U
|
||||
|
||||
/** @name Memory subtests
|
||||
* @{
|
||||
|
@ -135,12 +146,12 @@ extern "C" {
|
|||
/**
|
||||
* See the detailed description of the subtests in the file description.
|
||||
*/
|
||||
#define XIL_TESTMEM_ALLMEMTESTS 0
|
||||
#define XIL_TESTMEM_INCREMENT 1
|
||||
#define XIL_TESTMEM_WALKONES 2
|
||||
#define XIL_TESTMEM_WALKZEROS 3
|
||||
#define XIL_TESTMEM_INVERSEADDR 4
|
||||
#define XIL_TESTMEM_FIXEDPATTERN 5
|
||||
#define XIL_TESTMEM_ALLMEMTESTS 0x00U
|
||||
#define XIL_TESTMEM_INCREMENT 0x01U
|
||||
#define XIL_TESTMEM_WALKONES 0x02U
|
||||
#define XIL_TESTMEM_WALKZEROS 0x03U
|
||||
#define XIL_TESTMEM_INVERSEADDR 0x04U
|
||||
#define XIL_TESTMEM_FIXEDPATTERN 0x05U
|
||||
#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
|
||||
/* @} */
|
||||
|
||||
|
@ -151,9 +162,9 @@ extern "C" {
|
|||
|
||||
/* xutil_testmem prototypes */
|
||||
|
||||
extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
|
||||
extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
|
||||
extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
|
||||
extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
|
||||
extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
|
||||
extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
93
lib/bsp/standalone/src/common/xil_types.h
Executable file → Normal file
93
lib/bsp/standalone/src/common/xil_types.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -44,7 +55,9 @@
|
|||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a hbm 07/14/09 First release
|
||||
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
|
||||
* 4.2 srt 07/03/14 Use standard definitions from stdint.h
|
||||
* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
|
||||
* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
|
||||
* Define LONG and ULONG datatypes and mask values
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
@ -58,19 +71,19 @@
|
|||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#ifndef TRUE
|
||||
# define TRUE 1
|
||||
# define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
# define FALSE 0
|
||||
# define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */
|
||||
#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */
|
||||
#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */
|
||||
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */
|
||||
|
||||
/** @name New types
|
||||
* New simple types.
|
||||
|
@ -124,15 +137,27 @@ typedef struct
|
|||
/**
|
||||
* xbasic_types.h does not typedef s* or u64
|
||||
*/
|
||||
typedef uint64_t u64;
|
||||
|
||||
typedef char char8;
|
||||
typedef int8_t s8;
|
||||
typedef int16_t s16;
|
||||
typedef int32_t s32;
|
||||
typedef int64_t s64;
|
||||
typedef uint64_t u64;
|
||||
typedef int sint32;
|
||||
|
||||
typedef intptr_t INTPTR;
|
||||
typedef uintptr_t UINTPTR;
|
||||
typedef ptrdiff_t PTRDIFF;
|
||||
typedef ptrdiff_t PTRDIFF;
|
||||
|
||||
#if !defined(LONG) || !defined(ULONG)
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
#endif
|
||||
|
||||
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
|
||||
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
|
||||
|
||||
#else
|
||||
#include <linux/types.h>
|
||||
#endif
|
||||
|
@ -156,15 +181,15 @@ typedef void (*XExceptionHandler) (void *InstancePtr);
|
|||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
|
|
59
lib/bsp/standalone/src/common/xstatus.h
Executable file → Normal file
59
lib/bsp/standalone/src/common/xstatus.h
Executable file → Normal file
|
@ -1,32 +1,43 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
@ -416,7 +427,7 @@ extern "C" {
|
|||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
typedef int XStatus;
|
||||
typedef s32 XStatus;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
|
|
92
lib/bsp/standalone/src/cortexa53/gcc/Makefile
Normal file
92
lib/bsp/standalone/src/cortexa53/gcc/Makefile
Normal file
|
@ -0,0 +1,92 @@
|
|||
###############################################################################
|
||||
#
|
||||
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
# and is protected under U.S. and international copyright and other
|
||||
# intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any rights to the
|
||||
# materials distributed herewith. Except as otherwise provided in a valid
|
||||
# license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
# applicable law:
|
||||
# (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
# XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
# OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
# NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
# and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
# negligence, or under any other theory of liability) for any loss or damage of
|
||||
# any kind or nature related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect, special, incidental,
|
||||
# or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
# or any type of loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was reasonably foreseeable
|
||||
# or Xilinx had been advised of the possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
# any application requiring fail-safe performance, such as life-support or
|
||||
# safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any other applications
|
||||
# that could lead to death, personal injury, or severe property or environmental
|
||||
# damage (individually and collectively, "Critical Applications").
|
||||
# Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
# Critical Applications, subject only to applicable laws and regulations
|
||||
# governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
# AT ALL TIMES.
|
||||
#
|
||||
###############################################################################
|
||||
include config.make
|
||||
|
||||
AS=aarch64-none-elf-as
|
||||
CC=aarch64-none-elf-gcc
|
||||
AR=aarch64-none-elf-ar
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
LIB=libxil.a
|
||||
|
||||
CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
|
||||
ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
|
||||
|
||||
|
||||
#The following flags are required for PEEP. We can remove them later
|
||||
ECC_FLAGS += -march=armv8-a
|
||||
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
OUTS = *.o
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
|
||||
libs: $(LIBS)
|
||||
|
||||
standalone_libs: $(LIBSOURCES)
|
||||
echo "Compiling standalone A53"
|
||||
$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
|
||||
profile_libs:
|
||||
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" libs
|
||||
|
||||
.PHONY: include
|
||||
include: standalone_includes profile_includes
|
||||
|
||||
standalone_includes:
|
||||
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
|
||||
|
||||
profile_includes:
|
||||
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" include
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean
|
56
lib/bsp/standalone/src/cortexa53/gcc/_exit.c
Normal file
56
lib/bsp/standalone/src/cortexa53/gcc/_exit.c
Normal file
|
@ -0,0 +1,56 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <unistd.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
/* _exit - Simple implementation. Does not return.
|
||||
*/
|
||||
__attribute__((weak)) void _exit (sint32 status)
|
||||
{
|
||||
(void)status;
|
||||
while (1)
|
||||
{
|
||||
__asm__("wfi");
|
||||
}
|
||||
}
|
64
lib/bsp/standalone/src/cortexa53/gcc/_open.c
Normal file
64
lib/bsp/standalone/src/cortexa53/gcc/_open.c
Normal file
|
@ -0,0 +1,64 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <errno.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* _open -- open a file descriptor. We don't have a filesystem, so
|
||||
* we return an error.
|
||||
*/
|
||||
__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
|
||||
{
|
||||
(void *)buf;
|
||||
(void)flags;
|
||||
(void)mode;
|
||||
errno = EIO;
|
||||
return (-1);
|
||||
}
|
81
lib/bsp/standalone/src/cortexa53/gcc/_sbrk.c
Normal file
81
lib/bsp/standalone/src/cortexa53/gcc/_sbrk.c
Normal file
|
@ -0,0 +1,81 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <sys/types.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
extern u8 _heap_start[];
|
||||
extern u8 _heap_end[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) caddr_t _sbrk ( s32 incr );
|
||||
}
|
||||
#endif
|
||||
|
||||
__attribute__((weak)) caddr_t _sbrk ( s32 incr )
|
||||
{
|
||||
static u8 *heap = NULL;
|
||||
u8 *prev_heap;
|
||||
static u8 *HeapEndPtr = (u8 *)&_heap_end;
|
||||
caddr_t Status;
|
||||
|
||||
if (heap == NULL) {
|
||||
heap = (u8 *)&_heap_start;
|
||||
}
|
||||
prev_heap = heap;
|
||||
|
||||
heap += incr;
|
||||
|
||||
if (heap > HeapEndPtr){
|
||||
Status = (caddr_t) -1;
|
||||
}
|
||||
else if (prev_heap != NULL) {
|
||||
Status = (caddr_t) ((void *)prev_heap);
|
||||
}
|
||||
else {
|
||||
Status = (caddr_t) -1;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
53
lib/bsp/standalone/src/cortexa53/gcc/abort.c
Normal file
53
lib/bsp/standalone/src/cortexa53/gcc/abort.c
Normal file
|
@ -0,0 +1,53 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
|
||||
/*
|
||||
* abort -- go out via exit...
|
||||
*/
|
||||
__attribute__((weak)) void abort(void)
|
||||
{
|
||||
_exit(1);
|
||||
}
|
219
lib/bsp/standalone/src/cortexa53/gcc/asm_vectors.S
Normal file
219
lib/bsp/standalone/src/cortexa53/gcc/asm_vectors.S
Normal file
|
@ -0,0 +1,219 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file asm_vectors.s
|
||||
*
|
||||
* This file contains the initial vector table for the Cortex A53 processor
|
||||
* Currently NEON registers are not saved on stack if interrupt is taken.
|
||||
* It will be implemented.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 5/21/14 Initial version
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
|
||||
.org 0
|
||||
.text
|
||||
|
||||
.globl _boot
|
||||
.globl _vector_table
|
||||
|
||||
.globl FIQInterrupt
|
||||
.globl IRQInterrupt
|
||||
.globl SErrorInterrupt
|
||||
.globl SynchronousInterrupt
|
||||
|
||||
|
||||
.org 0
|
||||
|
||||
.section .vectors, "a"
|
||||
|
||||
_vector_table:
|
||||
|
||||
.set VBAR, _vector_table
|
||||
.org VBAR
|
||||
b _boot
|
||||
.org (VBAR + 0x200)
|
||||
b SynchronousInterruptHandler
|
||||
|
||||
.org (VBAR + 0x280)
|
||||
b IRQInterruptHandler
|
||||
|
||||
.org (VBAR + 0x300)
|
||||
b FIQInterruptHandler
|
||||
|
||||
.org (VBAR + 0x380)
|
||||
b SErrorInterruptHandler
|
||||
|
||||
|
||||
SynchronousInterruptHandler:
|
||||
stp X0,X1, [sp,#-0x10]!
|
||||
stp X2,X3, [sp,#-0x10]!
|
||||
stp X4,X5, [sp,#-0x10]!
|
||||
stp X6,X7, [sp,#-0x10]!
|
||||
stp X8,X9, [sp,#-0x10]!
|
||||
stp X10,X11, [sp,#-0x10]!
|
||||
stp X12,X13, [sp,#-0x10]!
|
||||
stp X14,X15, [sp,#-0x10]!
|
||||
stp X16,X17, [sp,#-0x10]!
|
||||
stp X18,X19, [sp,#-0x10]!
|
||||
stp X29,X30, [sp,#-0x10]!
|
||||
|
||||
bl SynchronousInterrupt
|
||||
|
||||
ldp X29,X30, [sp], #0x10
|
||||
ldp X18,X19, [sp], #0x10
|
||||
ldp X16,X17, [sp], #0x10
|
||||
ldp X14,X15, [sp], #0x10
|
||||
ldp X12,X13, [sp], #0x10
|
||||
ldp X10,X11, [sp], #0x10
|
||||
ldp X8,X9, [sp], #0x10
|
||||
ldp X6,X7, [sp], #0x10
|
||||
ldp X4,X5, [sp], #0x10
|
||||
ldp X2,X3, [sp], #0x10
|
||||
ldp X0,X1, [sp], #0x10
|
||||
|
||||
eret
|
||||
|
||||
IRQInterruptHandler:
|
||||
stp X0,X1, [sp,#-0x10]!
|
||||
stp X2,X3, [sp,#-0x10]!
|
||||
stp X4,X5, [sp,#-0x10]!
|
||||
stp X6,X7, [sp,#-0x10]!
|
||||
stp X8,X9, [sp,#-0x10]!
|
||||
stp X10,X11, [sp,#-0x10]!
|
||||
stp X12,X13, [sp,#-0x10]!
|
||||
stp X14,X15, [sp,#-0x10]!
|
||||
stp X16,X17, [sp,#-0x10]!
|
||||
stp X18,X19, [sp,#-0x10]!
|
||||
stp X29,X30, [sp,#-0x10]!
|
||||
|
||||
bl IRQInterrupt
|
||||
|
||||
ldp X29,X30, [sp], #0x10
|
||||
ldp X18,X19, [sp], #0x10
|
||||
ldp X16,X17, [sp], #0x10
|
||||
ldp X14,X15, [sp], #0x10
|
||||
ldp X12,X13, [sp], #0x10
|
||||
ldp X10,X11, [sp], #0x10
|
||||
ldp X8,X9, [sp], #0x10
|
||||
ldp X6,X7, [sp], #0x10
|
||||
ldp X4,X5, [sp], #0x10
|
||||
ldp X2,X3, [sp], #0x10
|
||||
ldp X0,X1, [sp], #0x10
|
||||
|
||||
eret
|
||||
|
||||
FIQInterruptHandler:
|
||||
|
||||
stp X0,X1, [sp,#-0x10]!
|
||||
stp X2,X3, [sp,#-0x10]!
|
||||
stp X4,X5, [sp,#-0x10]!
|
||||
stp X6,X7, [sp,#-0x10]!
|
||||
stp X8,X9, [sp,#-0x10]!
|
||||
stp X10,X11, [sp,#-0x10]!
|
||||
stp X12,X13, [sp,#-0x10]!
|
||||
stp X14,X15, [sp,#-0x10]!
|
||||
stp X16,X17, [sp,#-0x10]!
|
||||
stp X18,X19, [sp,#-0x10]!
|
||||
stp X29,X30, [sp,#-0x10]!
|
||||
|
||||
bl FIQInterrupt
|
||||
|
||||
ldp X29,X30, [sp], #0x10
|
||||
ldp X18,X19, [sp], #0x10
|
||||
ldp X16,X17, [sp], #0x10
|
||||
ldp X14,X15, [sp], #0x10
|
||||
ldp X12,X13, [sp], #0x10
|
||||
ldp X10,X11, [sp], #0x10
|
||||
ldp X8,X9, [sp], #0x10
|
||||
ldp X6,X7, [sp], #0x10
|
||||
ldp X4,X5, [sp], #0x10
|
||||
ldp X2,X3, [sp], #0x10
|
||||
ldp X0,X1, [sp], #0x10
|
||||
|
||||
eret
|
||||
|
||||
SErrorInterruptHandler:
|
||||
|
||||
stp X0,X1, [sp,#-0x10]!
|
||||
stp X2,X3, [sp,#-0x10]!
|
||||
stp X4,X5, [sp,#-0x10]!
|
||||
stp X6,X7, [sp,#-0x10]!
|
||||
stp X8,X9, [sp,#-0x10]!
|
||||
stp X10,X11, [sp,#-0x10]!
|
||||
stp X12,X13, [sp,#-0x10]!
|
||||
stp X14,X15, [sp,#-0x10]!
|
||||
stp X16,X17, [sp,#-0x10]!
|
||||
stp X18,X19, [sp,#-0x10]!
|
||||
stp X29,X30, [sp,#-0x10]!
|
||||
|
||||
bl SErrorInterrupt
|
||||
|
||||
ldp X29,X30, [sp], #0x10
|
||||
ldp X18,X19, [sp], #0x10
|
||||
ldp X16,X17, [sp], #0x10
|
||||
ldp X14,X15, [sp], #0x10
|
||||
ldp X12,X13, [sp], #0x10
|
||||
ldp X10,X11, [sp], #0x10
|
||||
ldp X8,X9, [sp], #0x10
|
||||
ldp X6,X7, [sp], #0x10
|
||||
ldp X4,X5, [sp], #0x10
|
||||
ldp X2,X3, [sp], #0x10
|
||||
ldp X0,X1, [sp], #0x10
|
||||
|
||||
eret
|
||||
|
||||
.end
|
275
lib/bsp/standalone/src/cortexa53/gcc/boot.S
Normal file
275
lib/bsp/standalone/src/cortexa53/gcc/boot.S
Normal file
|
@ -0,0 +1,275 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file boot.S
|
||||
*
|
||||
* This file contains the initial startup code for the Cortex A53 processor
|
||||
* Currently the processor starts at EL3 and boot code, startup and main
|
||||
* code will run on secure EL3.
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 5/21/14 Initial version
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
|
||||
.globl MMUTableL0
|
||||
.globl MMUTableL1
|
||||
.globl MMUTableL2
|
||||
.global _prestart
|
||||
.global _boot
|
||||
|
||||
.global __el3_stack
|
||||
.global __el2_stack
|
||||
.global __el1_stack
|
||||
.global __el0_stack
|
||||
.global _vector_table
|
||||
|
||||
|
||||
.set EL3_stack, __el3_stack
|
||||
.set EL2_stack, __el2_stack
|
||||
.set EL1_stack, __el1_stack
|
||||
.set EL0_stack, __el0_stack
|
||||
|
||||
.set TT_S1_FAULT, 0x0
|
||||
.set TT_S1_TABLE, 0x3
|
||||
|
||||
.set L0Table, MMUTableL0
|
||||
.set L1Table, MMUTableL1
|
||||
.set L2Table, MMUTableL2
|
||||
.set vector_base, _vector_table
|
||||
|
||||
.section .boot,"ax"
|
||||
|
||||
|
||||
/* this initializes the various processor modes */
|
||||
|
||||
_prestart:
|
||||
_boot:
|
||||
mov x0, #0
|
||||
mov x1, #0
|
||||
mov x2, #0
|
||||
mov x3, #0
|
||||
mov x4, #0
|
||||
mov x5, #0
|
||||
mov x6, #0
|
||||
mov x7, #0
|
||||
mov x8, #0
|
||||
mov x9, #0
|
||||
mov x10, #0
|
||||
mov x11, #0
|
||||
mov x12, #0
|
||||
mov x13, #0
|
||||
mov x14, #0
|
||||
mov x15, #0
|
||||
mov x16, #0
|
||||
mov x17, #0
|
||||
mov x18, #0
|
||||
mov x19, #0
|
||||
mov x20, #0
|
||||
mov x21, #0
|
||||
mov x22, #0
|
||||
mov x23, #0
|
||||
mov x24, #0
|
||||
mov x25, #0
|
||||
mov x26, #0
|
||||
mov x27, #0
|
||||
mov x28, #0
|
||||
mov x29, #0
|
||||
mov x30, #0
|
||||
#if 0 //dont put other a53 cpus in wfi
|
||||
//Which core am I
|
||||
// ----------------
|
||||
mrs x0, MPIDR_EL1
|
||||
and x0, x0, #0xFF //Mask off to leave Aff0
|
||||
cbz x0, OKToRun //If core 0, run the primary init code
|
||||
EndlessLoop0:
|
||||
wfi
|
||||
b EndlessLoop0
|
||||
#endif
|
||||
OKToRun:
|
||||
|
||||
/*Set vector table base address*/
|
||||
ldr x1, =vector_base
|
||||
msr VBAR_EL3,x1
|
||||
|
||||
/*Define stack pointer for current exception level*/
|
||||
ldr x2,=EL3_stack
|
||||
mov sp,x2
|
||||
|
||||
|
||||
/* Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU*/
|
||||
mov x0, #0 // Clear all trap bits
|
||||
msr CPTR_EL3, x0
|
||||
|
||||
|
||||
/* Configure SCR_EL3 */
|
||||
mov w1, #0 //; Initial value of register is unknown
|
||||
orr w1, w1, #(1 << 11) //; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
|
||||
orr w1, w1, #(1 << 10) //; Set RW bit (EL1 is AArch64, as this is the Secure world)
|
||||
orr w1, w1, #(1 << 3) //; Set EA bit (SError routed to EL3)
|
||||
orr w1, w1, #(1 << 2) //; Set FIQ bit (FIQs routed to EL3)
|
||||
orr w1, w1, #(1 << 1) //; Set IRQ bit (IRQs routed to EL3)
|
||||
msr SCR_EL3, x1
|
||||
|
||||
/*Enable ECC protection*/
|
||||
mrs x0, S3_1_C11_C0_2 // register L2CTLR_EL1
|
||||
orr x0, x0, #(1<<22)
|
||||
msr S3_1_C11_C0_2, x0
|
||||
|
||||
/*configure cpu auxiliary control register EL1 */
|
||||
ldr x0,=0x80CA000 // L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
|
||||
msr S3_1_C15_C2_0, x0 //CPUACTLR_EL1
|
||||
|
||||
|
||||
/*Enable hardware coherency between cores*/
|
||||
mrs x0, S3_1_c15_c2_1 //Read EL1 CPU Extended Control Register
|
||||
orr x0, x0, #(1 << 6) //Set the SMPEN bit
|
||||
msr S3_1_c15_c2_1, x0 //Write EL1 CPU Extended Control Register
|
||||
isb
|
||||
|
||||
tlbi ALLE3
|
||||
ic IALLU //; Invalidate I cache to PoU
|
||||
bl invalidate_dcaches
|
||||
dsb sy
|
||||
isb
|
||||
|
||||
ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL1
|
||||
msr TTBR0_EL3, x1 //; Set TTBR0_EL3 (NOTE: There is no TTBR1 at EL1)
|
||||
|
||||
|
||||
/**********************************************
|
||||
* Set up memory attributes
|
||||
* This equates to:
|
||||
* 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
|
||||
* 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
|
||||
* 2 = b00000000 = Device-nGnRnE
|
||||
**********************************************/
|
||||
ldr x1, =0x000000000000FF44
|
||||
msr MAIR_EL3, x1
|
||||
|
||||
/**********************************************
|
||||
* Set up TCR_EL1
|
||||
* ---------------
|
||||
***************************************************/
|
||||
ldr x1,=0x80803518 /*40 bit*/
|
||||
msr TCR_EL3, x1
|
||||
isb
|
||||
|
||||
/* Configure SCTLR_EL3 */
|
||||
mov x1, #0 //Most of the SCTLR_EL3 bits are unknown at reset
|
||||
orr x1, x1, #(1 << 12) //Enable I cache
|
||||
orr x1, x1, #(1 << 3) //Enable SP alignment check
|
||||
orr x1, x1, #(1 << 2) //Enable caches
|
||||
orr x1, x1, #(1 << 1) //Enable alignment
|
||||
orr x1, x1, #(1 << 0) //Enable MMU
|
||||
msr SCTLR_EL3, x1
|
||||
dsb sy
|
||||
isb
|
||||
|
||||
bl _startup //jump to start
|
||||
|
||||
loop: b loop
|
||||
|
||||
|
||||
invalidate_dcaches:
|
||||
|
||||
dmb ISH
|
||||
mrs x0, CLIDR_EL1 //; x0 = CLIDR
|
||||
ubfx w2, w0, #24, #3 //; w2 = CLIDR.LoC
|
||||
cmp w2, #0 //; LoC is 0?
|
||||
b.eq invalidateCaches_end //; No cleaning required and enable MMU
|
||||
mov w1, #0 //; w1 = level iterator
|
||||
|
||||
invalidateCaches_flush_level:
|
||||
add w3, w1, w1, lsl #1 //; w3 = w1 * 3 (right-shift for cache type)
|
||||
lsr w3, w0, w3 //; w3 = w0 >> w3
|
||||
ubfx w3, w3, #0, #3 //; w3 = cache type of this level
|
||||
cmp w3, #2 //; No cache at this level?
|
||||
b.lt invalidateCaches_next_level
|
||||
|
||||
lsl w4, w1, #1
|
||||
msr CSSELR_EL1, x4 //; Select current cache level in CSSELR
|
||||
isb //; ISB required to reflect new CSIDR
|
||||
mrs x4, CCSIDR_EL1 //; w4 = CSIDR
|
||||
|
||||
ubfx w3, w4, #0, #3
|
||||
add w3, w3, #2 //; w3 = log2(line size)
|
||||
ubfx w5, w4, #13, #15
|
||||
ubfx w4, w4, #3, #10 //; w4 = Way number
|
||||
clz w6, w4 //; w6 = 32 - log2(number of ways)
|
||||
|
||||
invalidateCaches_flush_set:
|
||||
mov w8, w4 //; w8 = Way number
|
||||
invalidateCaches_flush_way:
|
||||
lsl w7, w1, #1 //; Fill level field
|
||||
lsl w9, w5, w3
|
||||
orr w7, w7, w9 //; Fill index field
|
||||
lsl w9, w8, w6
|
||||
orr w7, w7, w9 //; Fill way field
|
||||
dc CISW, x7 //; Invalidate by set/way to point of coherency
|
||||
subs w8, w8, #1 //; Decrement way
|
||||
b.ge invalidateCaches_flush_way
|
||||
subs w5, w5, #1 //; Descrement set
|
||||
b.ge invalidateCaches_flush_set
|
||||
|
||||
invalidateCaches_next_level:
|
||||
add w1, w1, #1 //; Next level
|
||||
cmp w2, w1
|
||||
b.gt invalidateCaches_flush_level
|
||||
|
||||
invalidateCaches_end:
|
||||
ret
|
||||
|
||||
.end
|
58
lib/bsp/standalone/src/cortexa53/gcc/close.c
Normal file
58
lib/bsp/standalone/src/cortexa53/gcc/close.c
Normal file
|
@ -0,0 +1,58 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
#include "xil_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) s32 _close(s32 fd);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* close -- We don't need to do anything, but pretend we did.
|
||||
*/
|
||||
|
||||
__attribute__((weak)) s32 _close(s32 fd)
|
||||
{
|
||||
(void)fd;
|
||||
return (0);
|
||||
}
|
62
lib/bsp/standalone/src/cortexa53/gcc/errno.c
Normal file
62
lib/bsp/standalone/src/cortexa53/gcc/errno.c
Normal file
|
@ -0,0 +1,62 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* The errno variable is stored in the reentrancy structure. This
|
||||
function returns its address for use by the macro errno defined in
|
||||
errno.h. */
|
||||
|
||||
#include <errno.h>
|
||||
#include <reent.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) sint32 * __errno (void);
|
||||
}
|
||||
#endif
|
||||
|
||||
__attribute__((weak)) sint32 *
|
||||
__errno (void)
|
||||
{
|
||||
return &_REENT->_errno;
|
||||
}
|
57
lib/bsp/standalone/src/cortexa53/gcc/fcntl.c
Normal file
57
lib/bsp/standalone/src/cortexa53/gcc/fcntl.c
Normal file
|
@ -0,0 +1,57 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
/*
|
||||
* fcntl -- Manipulate a file descriptor.
|
||||
* We don't have a filesystem, so we do nothing.
|
||||
*/
|
||||
__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg)
|
||||
{
|
||||
(void)fd;
|
||||
(void)cmd;
|
||||
(void)arg;
|
||||
return 0;
|
||||
}
|
61
lib/bsp/standalone/src/cortexa53/gcc/fstat.c
Normal file
61
lib/bsp/standalone/src/cortexa53/gcc/fstat.c
Normal file
|
@ -0,0 +1,61 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* fstat -- Since we have no file system, we just return an error.
|
||||
*/
|
||||
__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
|
||||
{
|
||||
(void)fd;
|
||||
buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
|
||||
|
||||
return (0);
|
||||
}
|
62
lib/bsp/standalone/src/cortexa53/gcc/getpid.c
Normal file
62
lib/bsp/standalone/src/cortexa53/gcc/getpid.c
Normal file
|
@ -0,0 +1,62 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
/*
|
||||
* getpid -- only one process, so just return 1.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) s32 _getpid(void);
|
||||
}
|
||||
#endif
|
||||
|
||||
__attribute__((weak)) s32 getpid(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) s32 _getpid(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
|
@ -0,0 +1,63 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file initialise_monitor_handles.c
|
||||
*
|
||||
* Contains blank function to avoid compilation error
|
||||
*
|
||||
* @note
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
__attribute__((weak)) void initialise_monitor_handles(){
|
||||
|
||||
}
|
67
lib/bsp/standalone/src/cortexa53/gcc/isatty.c
Normal file
67
lib/bsp/standalone/src/cortexa53/gcc/isatty.c
Normal file
|
@ -0,0 +1,67 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
#include <unistd.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) sint32 _isatty(sint32 fd);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* isatty -- returns 1 if connected to a terminal device,
|
||||
* returns 0 if not. Since we're hooked up to a
|
||||
* serial port, we'll say yes _AND return a 1.
|
||||
*/
|
||||
__attribute__((weak)) sint32 isatty(sint32 fd)
|
||||
{
|
||||
(void)fd;
|
||||
return (1);
|
||||
}
|
||||
|
||||
__attribute__((weak)) sint32 _isatty(sint32 fd)
|
||||
{
|
||||
(void)fd;
|
||||
return (1);
|
||||
}
|
71
lib/bsp/standalone/src/cortexa53/gcc/kill.c
Normal file
71
lib/bsp/standalone/src/cortexa53/gcc/kill.c
Normal file
|
@ -0,0 +1,71 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
#include <signal.h>
|
||||
#include <unistd.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) s32 _kill(s32 pid, s32 sig);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* kill -- go out via exit...
|
||||
*/
|
||||
|
||||
__attribute__((weak)) s32 kill(s32 pid, s32 sig)
|
||||
{
|
||||
if(pid == 1) {
|
||||
_exit(sig);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((weak)) s32 _kill(s32 pid, s32 sig)
|
||||
{
|
||||
if(pid == 1) {
|
||||
_exit(sig);
|
||||
}
|
||||
return 0;
|
||||
}
|
72
lib/bsp/standalone/src/cortexa53/gcc/lseek.c
Normal file
72
lib/bsp/standalone/src/cortexa53/gcc/lseek.c
Normal file
|
@ -0,0 +1,72 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <errno.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* lseek -- Since a serial port is non-seekable, we return an error.
|
||||
*/
|
||||
__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
|
||||
{
|
||||
(void)fd;
|
||||
(void)offset;
|
||||
(void)whence;
|
||||
errno = ESPIPE;
|
||||
return ((off_t)-1);
|
||||
}
|
||||
|
||||
__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
|
||||
{
|
||||
(void)fd;
|
||||
(void)offset;
|
||||
(void)whence;
|
||||
errno = ESPIPE;
|
||||
return ((off_t)-1);
|
||||
}
|
326
lib/bsp/standalone/src/cortexa53/gcc/memfun.c
Normal file
326
lib/bsp/standalone/src/cortexa53/gcc/memfun.c
Normal file
|
@ -0,0 +1,326 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose without fee is hereby granted, provided that this entire notice is
|
||||
* included in all copies of any software which is or includes a copy or
|
||||
* modification of this software and in all copies of the supporting
|
||||
* documentation for such software.
|
||||
*
|
||||
* THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR
|
||||
* IMPLIED WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T
|
||||
* MAKES ANY REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING
|
||||
* THE MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR
|
||||
* PURPOSE.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
FUNCTION
|
||||
<<memset>>---set an area of memory
|
||||
|
||||
INDEX
|
||||
memset
|
||||
|
||||
ANSI_SYNOPSIS
|
||||
#include <string.h>
|
||||
void *memset(void *<[dst]>, int <[c]>, size_t <[length]>);
|
||||
|
||||
TRAD_SYNOPSIS
|
||||
#include <string.h>
|
||||
void *memset(<[dst]>, <[c]>, <[length]>)
|
||||
void *<[dst]>;
|
||||
int <[c]>;
|
||||
size_t <[length]>;
|
||||
|
||||
DESCRIPTION
|
||||
This function converts the argument <[c]> into an unsigned
|
||||
char and fills the first <[length]> characters of the array
|
||||
pointed to by <[dst]> to the value.
|
||||
|
||||
RETURNS
|
||||
<<memset>> returns the value of <[dst]>.
|
||||
|
||||
PORTABILITY
|
||||
<<memset>> is ANSI C.
|
||||
|
||||
<<memset>> requires no supporting OS subroutines.
|
||||
|
||||
QUICKREF
|
||||
memset ansi pure
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <_ansi.h>
|
||||
|
||||
#define LBLOCKSIZE (sizeof(long))
|
||||
#define UNALIGNED_S(X) ((long)X & (LBLOCKSIZE - 1))
|
||||
#define TOO_SMALL(LEN) ((LEN) < LBLOCKSIZE)
|
||||
|
||||
/* Nonzero if either X or Y is not aligned on a "long" boundary. */
|
||||
#define UNALIGNED(X, Y) \
|
||||
(((long)X & (sizeof (long) - 1)) | ((long)Y & (sizeof (long) - 1)))
|
||||
|
||||
/* How many bytes are copied each iteration of the 4X unrolled loop. */
|
||||
#define BIGBLOCKSIZE (sizeof (long) << 2)
|
||||
|
||||
/* How many bytes are copied each iteration of the word copy loop. */
|
||||
#define LITTLEBLOCKSIZE (sizeof (long))
|
||||
|
||||
|
||||
_PTR
|
||||
_DEFUN (memset, (m, c, n),
|
||||
_PTR m _AND
|
||||
int c _AND
|
||||
size_t n)
|
||||
{
|
||||
char *s = (char *) m;
|
||||
|
||||
#if !defined(PREFER_SIZE_OVER_SPEED) && !defined(__OPTIMIZE_SIZE__)
|
||||
int i;
|
||||
unsigned long buffer;
|
||||
unsigned long *aligned_addr;
|
||||
unsigned int d = c & 0xff; /* To avoid sign extension, copy C to an
|
||||
unsigned variable. */
|
||||
|
||||
while (UNALIGNED_S (s))
|
||||
{
|
||||
if (n--)
|
||||
*s++ = (char) c;
|
||||
else
|
||||
return m;
|
||||
}
|
||||
|
||||
if (!TOO_SMALL (n))
|
||||
{
|
||||
/* If we get this far, we know that n is large and s is word-aligned. */
|
||||
aligned_addr = (unsigned long *) s;
|
||||
|
||||
/* Store D into each char sized location in BUFFER so that
|
||||
we can set large blocks quickly. */
|
||||
buffer = (d << 8) | d;
|
||||
buffer |= (buffer << 16);
|
||||
for (i = 32; i < LBLOCKSIZE * 8; i <<= 1)
|
||||
buffer = (buffer << i) | buffer;
|
||||
|
||||
/* Unroll the loop. */
|
||||
while (n >= LBLOCKSIZE*4)
|
||||
{
|
||||
*aligned_addr++ = buffer;
|
||||
*aligned_addr++ = buffer;
|
||||
*aligned_addr++ = buffer;
|
||||
*aligned_addr++ = buffer;
|
||||
n -= 4*LBLOCKSIZE;
|
||||
}
|
||||
|
||||
while (n >= LBLOCKSIZE)
|
||||
{
|
||||
*aligned_addr++ = buffer;
|
||||
n -= LBLOCKSIZE;
|
||||
}
|
||||
/* Pick up the remainder with a bytewise loop. */
|
||||
s = (char*)aligned_addr;
|
||||
}
|
||||
|
||||
#endif /* not PREFER_SIZE_OVER_SPEED */
|
||||
|
||||
while (n--)
|
||||
*s++ = (char) c;
|
||||
|
||||
return m;
|
||||
}
|
||||
|
||||
/*
|
||||
FUNCTION
|
||||
<<memcmp>>---compare two memory areas
|
||||
|
||||
INDEX
|
||||
memcmp
|
||||
|
||||
ANSI_SYNOPSIS
|
||||
#include <string.h>
|
||||
int memcmp(const void *<[s1]>, const void *<[s2]>, size_t <[n]>);
|
||||
|
||||
TRAD_SYNOPSIS
|
||||
#include <string.h>
|
||||
int memcmp(<[s1]>, <[s2]>, <[n]>)
|
||||
void *<[s1]>;
|
||||
void *<[s2]>;
|
||||
size_t <[n]>;
|
||||
|
||||
DESCRIPTION
|
||||
This function compares not more than <[n]> characters of the
|
||||
object pointed to by <[s1]> with the object pointed to by <[s2]>.
|
||||
|
||||
|
||||
RETURNS
|
||||
The function returns an integer greater than, equal to or
|
||||
less than zero according to whether the object pointed to by
|
||||
<[s1]> is greater than, equal to or less than the object
|
||||
pointed to by <[s2]>.
|
||||
|
||||
PORTABILITY
|
||||
<<memcmp>> is ANSI C.
|
||||
|
||||
<<memcmp>> requires no supporting OS subroutines.
|
||||
|
||||
QUICKREF
|
||||
memcmp ansi pure
|
||||
*/
|
||||
|
||||
|
||||
|
||||
int
|
||||
_DEFUN (memcmp, (m1, m2, n),
|
||||
_CONST _PTR m1 _AND
|
||||
_CONST _PTR m2 _AND
|
||||
size_t n)
|
||||
{
|
||||
#if defined(PREFER_SIZE_OVER_SPEED) || defined(__OPTIMIZE_SIZE__)
|
||||
unsigned char *s1 = (unsigned char *) m1;
|
||||
unsigned char *s2 = (unsigned char *) m2;
|
||||
|
||||
while (n--)
|
||||
{
|
||||
if (*s1 != *s2)
|
||||
{
|
||||
return *s1 - *s2;
|
||||
}
|
||||
s1++;
|
||||
s2++;
|
||||
}
|
||||
return 0;
|
||||
#else
|
||||
unsigned char *s1 = (unsigned char *) m1;
|
||||
unsigned char *s2 = (unsigned char *) m2;
|
||||
unsigned long *a1;
|
||||
unsigned long *a2;
|
||||
|
||||
/* If the size is too small, or either pointer is unaligned,
|
||||
then we punt to the byte compare loop. Hopefully this will
|
||||
not turn up in inner loops. */
|
||||
if (!TOO_SMALL(n) && !UNALIGNED(s1,s2))
|
||||
{
|
||||
/* Otherwise, load and compare the blocks of memory one
|
||||
word at a time.*/
|
||||
a1 = (unsigned long*) s1;
|
||||
a2 = (unsigned long*) s2;
|
||||
while (n >= LBLOCKSIZE)
|
||||
{
|
||||
if (*a1 != *a2)
|
||||
break;
|
||||
a1++;
|
||||
a2++;
|
||||
n -= LBLOCKSIZE;
|
||||
}
|
||||
/* check m mod LBLOCKSIZE remaining characters */
|
||||
|
||||
s1 = (unsigned char*)a1;
|
||||
s2 = (unsigned char*)a2;
|
||||
}
|
||||
|
||||
while (n--)
|
||||
{
|
||||
if (*s1 != *s2)
|
||||
return *s1 - *s2;
|
||||
s1++;
|
||||
s2++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
#endif /* not PREFER_SIZE_OVER_SPEED */
|
||||
}
|
||||
|
||||
/*
|
||||
FUNCTION
|
||||
<<memcpy>>---copy memory regions
|
||||
|
||||
ANSI_SYNOPSIS
|
||||
#include <string.h>
|
||||
void* memcpy(void *<[out]>, const void *<[in]>, size_t <[n]>);
|
||||
|
||||
TRAD_SYNOPSIS
|
||||
#include <string.h>
|
||||
void *memcpy(<[out]>, <[in]>, <[n]>
|
||||
void *<[out]>;
|
||||
void *<[in]>;
|
||||
size_t <[n]>;
|
||||
|
||||
DESCRIPTION
|
||||
This function copies <[n]> bytes from the memory region
|
||||
pointed to by <[in]> to the memory region pointed to by
|
||||
<[out]>.
|
||||
|
||||
If the regions overlap, the behavior is undefined.
|
||||
|
||||
RETURNS
|
||||
<<memcpy>> returns a pointer to the first byte of the <[out]>
|
||||
region.
|
||||
|
||||
PORTABILITY
|
||||
<<memcpy>> is ANSI C.
|
||||
|
||||
<<memcpy>> requires no supporting OS subroutines.
|
||||
|
||||
QUICKREF
|
||||
memcpy ansi pure
|
||||
*/
|
||||
|
||||
|
||||
_PTR
|
||||
_DEFUN (memcpy, (dst0, src0, len0),
|
||||
_PTR dst0 _AND
|
||||
_CONST _PTR src0 _AND
|
||||
size_t len0)
|
||||
{
|
||||
#if defined(PREFER_SIZE_OVER_SPEED) || defined(__OPTIMIZE_SIZE__)
|
||||
char *dst = (char *) dst0;
|
||||
char *src = (char *) src0;
|
||||
|
||||
_PTR save = dst0;
|
||||
|
||||
while (len0--)
|
||||
{
|
||||
*dst++ = *src++;
|
||||
}
|
||||
|
||||
return save;
|
||||
#else
|
||||
char *dst = dst0;
|
||||
_CONST char *src = src0;
|
||||
long *aligned_dst;
|
||||
_CONST long *aligned_src;
|
||||
|
||||
/* If the size is small, or either SRC or DST is unaligned,
|
||||
then punt into the byte copy loop. This should be rare. */
|
||||
if (!TOO_SMALL(len0) && !UNALIGNED (src, dst))
|
||||
{
|
||||
aligned_dst = (long*)dst;
|
||||
aligned_src = (long*)src;
|
||||
|
||||
/* Copy 4X long words at a time if possible. */
|
||||
while (len0 >= BIGBLOCKSIZE)
|
||||
{
|
||||
*aligned_dst++ = *aligned_src++;
|
||||
*aligned_dst++ = *aligned_src++;
|
||||
*aligned_dst++ = *aligned_src++;
|
||||
*aligned_dst++ = *aligned_src++;
|
||||
len0 -= BIGBLOCKSIZE;
|
||||
}
|
||||
|
||||
/* Copy one long word at a time if possible. */
|
||||
while (len0 >= LITTLEBLOCKSIZE)
|
||||
{
|
||||
*aligned_dst++ = *aligned_src++;
|
||||
len0 -= LITTLEBLOCKSIZE;
|
||||
}
|
||||
|
||||
/* Pick up any residual with a byte copier. */
|
||||
dst = (char*)aligned_dst;
|
||||
src = (char*)aligned_src;
|
||||
}
|
||||
|
||||
while (len0--)
|
||||
*dst++ = *src++;
|
||||
|
||||
return dst0;
|
||||
#endif /* not PREFER_SIZE_OVER_SPEED */
|
||||
}
|
63
lib/bsp/standalone/src/cortexa53/gcc/open.c
Normal file
63
lib/bsp/standalone/src/cortexa53/gcc/open.c
Normal file
|
@ -0,0 +1,63 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <errno.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* open -- open a file descriptor. We don't have a filesystem, so
|
||||
* we return an error.
|
||||
*/
|
||||
__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode)
|
||||
{
|
||||
(void *)buf;
|
||||
(void)flags;
|
||||
(void)mode;
|
||||
errno = EIO;
|
||||
return (-1);
|
||||
}
|
122
lib/bsp/standalone/src/cortexa53/gcc/read.c
Normal file
122
lib/bsp/standalone/src/cortexa53/gcc/read.c
Normal file
|
@ -0,0 +1,122 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* read.c -- read bytes from a input device.
|
||||
*/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xil_printf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* read -- read bytes from the serial port. Ignore fd, since
|
||||
* we only have stdin.
|
||||
*/
|
||||
__attribute__((weak)) s32
|
||||
read (s32 fd, char8* buf, s32 nbytes)
|
||||
{
|
||||
#ifdef STDIN_BASEADDRESS
|
||||
s32 i;
|
||||
char8* LocalBuf = buf;
|
||||
|
||||
(void)fd;
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf += i;
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
*LocalBuf = inbyte();
|
||||
if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf -= i;
|
||||
}
|
||||
}
|
||||
|
||||
return (i + 1);
|
||||
#else
|
||||
(void)fd;
|
||||
(void)buf;
|
||||
(void)nbytes;
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
__attribute__((weak)) s32
|
||||
_read (s32 fd, char8* buf, s32 nbytes)
|
||||
{
|
||||
#ifdef STDIN_BASEADDRESS
|
||||
s32 i;
|
||||
char8* LocalBuf = buf;
|
||||
|
||||
(void)fd;
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf += i;
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
*LocalBuf = inbyte();
|
||||
if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf -= i;
|
||||
}
|
||||
}
|
||||
|
||||
return (i + 1);
|
||||
#else
|
||||
(void)fd;
|
||||
(void)buf;
|
||||
(void)nbytes;
|
||||
return 0;
|
||||
#endif
|
||||
}
|
76
lib/bsp/standalone/src/cortexa53/gcc/sbrk.c
Normal file
76
lib/bsp/standalone/src/cortexa53/gcc/sbrk.c
Normal file
|
@ -0,0 +1,76 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <errno.h>
|
||||
#include "xil_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) char8 *sbrk (s32 nbytes);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern u8 _heap_start[];
|
||||
extern u8 _heap_end[];
|
||||
extern char8 HeapBase[];
|
||||
extern char8 HeapLimit[];
|
||||
|
||||
|
||||
|
||||
__attribute__((weak)) char8 *sbrk (s32 nbytes)
|
||||
{
|
||||
char8 *base;
|
||||
static char8 *heap_ptr = HeapBase;
|
||||
|
||||
base = heap_ptr;
|
||||
if(heap_ptr != NULL) {
|
||||
heap_ptr += nbytes;
|
||||
}
|
||||
|
||||
/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
|
||||
if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
|
||||
return base;
|
||||
} else {
|
||||
errno = ENOMEM;
|
||||
return ((char8 *)-1);
|
||||
}
|
||||
}
|
181
lib/bsp/standalone/src/cortexa53/gcc/translation_table.s
Normal file
181
lib/bsp/standalone/src/cortexa53/gcc/translation_table.s
Normal file
|
@ -0,0 +1,181 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file translation_table.s
|
||||
*
|
||||
* This file contains the initialization for the MMU table in RAM
|
||||
* needed by the Cortex A53 processor
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/21/14 Initial version
|
||||
*
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
.globl MMUTableL0
|
||||
.globl MMUTableL1
|
||||
.globl MMUTableL2
|
||||
|
||||
.set reserved, 0x0 /* Fault*/
|
||||
.set Memory, 0x405 | (3 << 8) | (0x0) /* normal writeback write allocate inner shared read write */
|
||||
.set Device, 0x409 | (1 << 53)| (1 << 54) |(0x0) /* strongly ordered read write non executable*/
|
||||
.section .mmu_tbl0,"a"
|
||||
|
||||
MMUTableL0:
|
||||
|
||||
.set SECT, MMUTableL1
|
||||
.8byte SECT + 0x3
|
||||
.set SECT, MMUTableL1+0x1000
|
||||
.8byte SECT + 0x3
|
||||
|
||||
.section .mmu_tbl1,"a"
|
||||
|
||||
MMUTableL1:
|
||||
|
||||
.set SECT, MMUTableL2 /*1GB DDR*/
|
||||
.8byte SECT + 0x3
|
||||
|
||||
.rept 0x3 /*1GB DDR, 1GB PL, 2GB other devices n memory*/
|
||||
.set SECT, SECT + 0x1000
|
||||
.8byte SECT + 0x3
|
||||
.endr
|
||||
|
||||
.set SECT,0x100000000
|
||||
.rept 0xC
|
||||
.8byte SECT + reserved
|
||||
.set SECT, SECT + 0x40000000 /*12GB Reserved*/
|
||||
.endr
|
||||
|
||||
.rept 0x10
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT + 0x40000000 /*8GB PL, 8GB PCIe*/
|
||||
|
||||
.endr
|
||||
|
||||
.rept 0x20
|
||||
.8byte SECT + Memory
|
||||
|
||||
.set SECT, SECT + 0x40000000 /*32GB DDR*/
|
||||
.endr
|
||||
|
||||
|
||||
.rept 0xC0
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT + 0x40000000 /*192GB PL*/
|
||||
.endr
|
||||
|
||||
|
||||
.rept 0x100
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT + 0x40000000 /*256GB PL/PCIe*/
|
||||
.endr
|
||||
|
||||
|
||||
.rept 0x200
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT + 0x40000000 /*512GB PL/DDR*/
|
||||
.endr
|
||||
|
||||
|
||||
.section .mmu_tbl2,"a"
|
||||
|
||||
MMUTableL2:
|
||||
|
||||
.set SECT, 0
|
||||
|
||||
.rept 0x0400 /*2GB DDR */
|
||||
.8byte SECT + Memory
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
|
||||
.rept 0x0200 /*1GB lower PL*/
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
.rept 0x0100 /*512MB QSPI*/
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
.rept 0x080 /*256MB lower PCIe*/
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
.rept 0x040 /*128MB Reserved*/
|
||||
.8byte SECT + reserved
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
.rept 0x8 /*16MB coresight*/
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
.rept 0x8 /*16MB RPU low latency port*/
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
|
||||
.rept 0x022 /*68MB Device*/
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
.rept 0x8 /*8MB FPS*/
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
|
||||
.rept 0x4 /*16MB LPS*/
|
||||
.8byte SECT + Device
|
||||
.set SECT, SECT+0x200000
|
||||
.endr
|
||||
|
||||
.8byte SECT + Device /*2MB PMU/CSU */
|
||||
.set SECT, SECT+0x200000
|
||||
.8byte SECT + Memory /*2MB OCM/TCM*/
|
||||
.end
|
61
lib/bsp/standalone/src/cortexa53/gcc/unlink.c
Normal file
61
lib/bsp/standalone/src/cortexa53/gcc/unlink.c
Normal file
|
@ -0,0 +1,61 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <errno.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) s32 unlink(char8 *path);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* unlink -- since we have no file system,
|
||||
* we just return an error.
|
||||
*/
|
||||
__attribute__((weak)) s32 unlink(char8 *path)
|
||||
{
|
||||
(void *)path;
|
||||
errno = EIO;
|
||||
return (-1);
|
||||
}
|
122
lib/bsp/standalone/src/cortexa53/gcc/write.c
Normal file
122
lib/bsp/standalone/src/cortexa53/gcc/write.c
Normal file
|
@ -0,0 +1,122 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* write.c -- write bytes to an output device.
|
||||
*/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xil_printf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* write -- write bytes to the serial port. Ignore fd, since
|
||||
* stdout and stderr are the same. Since we have no filesystem,
|
||||
* open will only return an error.
|
||||
*/
|
||||
__attribute__((weak)) s32
|
||||
write (s32 fd, char8* buf, s32 nbytes)
|
||||
|
||||
{
|
||||
#ifdef STDOUT_BASEADDRESS
|
||||
s32 i;
|
||||
char8* LocalBuf = buf;
|
||||
|
||||
(void)fd;
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf += i;
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
if (*LocalBuf == '\n') {
|
||||
outbyte ('\r');
|
||||
}
|
||||
outbyte (*LocalBuf);
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf -= i;
|
||||
}
|
||||
}
|
||||
return (nbytes);
|
||||
#else
|
||||
(void)fd;
|
||||
(void)buf;
|
||||
(void)nbytes;
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
__attribute__((weak)) s32
|
||||
_write (s32 fd, char8* buf, s32 nbytes)
|
||||
{
|
||||
#ifdef STDOUT_BASEADDRESS
|
||||
s32 i;
|
||||
char8* LocalBuf = buf;
|
||||
|
||||
(void)fd;
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf += i;
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
if (*LocalBuf == '\n') {
|
||||
outbyte ('\r');
|
||||
}
|
||||
outbyte (*LocalBuf);
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf -= i;
|
||||
}
|
||||
}
|
||||
return (nbytes);
|
||||
#else
|
||||
(void)fd;
|
||||
(void)buf;
|
||||
(void)nbytes;
|
||||
return 0;
|
||||
#endif
|
||||
}
|
132
lib/bsp/standalone/src/cortexa53/gcc/xil-crt0.S
Normal file
132
lib/bsp/standalone/src/cortexa53/gcc/xil-crt0.S
Normal file
|
@ -0,0 +1,132 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xil-crt0.S
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/21/14 Initial version
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
.extern XSmc_NorInit
|
||||
.extern XSmc_SramInit
|
||||
|
||||
.file "xil-crt0.S"
|
||||
.section ".got2","aw"
|
||||
.align 2
|
||||
|
||||
.text
|
||||
.Lsbss_start:
|
||||
.long __sbss_start
|
||||
|
||||
.Lsbss_end:
|
||||
.long __sbss_end
|
||||
|
||||
.Lbss_start:
|
||||
.long __bss_start__
|
||||
|
||||
.Lbss_end:
|
||||
.long __bss_end__
|
||||
|
||||
|
||||
|
||||
.globl _startup
|
||||
_startup:
|
||||
|
||||
mov x0, #0
|
||||
|
||||
/* clear sbss */
|
||||
ldr w1,.Lsbss_start /* calculate beginning of the SBSS */
|
||||
ldr w2,.Lsbss_end /* calculate end of the SBSS */
|
||||
uxtw x1, w1 /*zero extension to w1 register*/
|
||||
uxtw x2, w2 /*zero extension to w2 register*/
|
||||
|
||||
.Lloop_sbss:
|
||||
cmp x1,x2
|
||||
bge .Lenclsbss /* If no SBSS, no clearing required */
|
||||
str x0, [x1], #8
|
||||
b .Lloop_sbss
|
||||
|
||||
.Lenclsbss:
|
||||
/* clear bss */
|
||||
ldr w1,.Lbss_start /* calculate beginning of the BSS */
|
||||
ldr w2,.Lbss_end /* calculate end of the BSS */
|
||||
uxtw x1, w1 /*zero extension to w1 register*/
|
||||
uxtw x2, w2 /*zero extension to w2 register*/
|
||||
|
||||
.Lloop_bss:
|
||||
cmp x1,x2
|
||||
bge .Lenclbss /* If no BSS, no clearing required */
|
||||
str x0, [x1], #8
|
||||
b .Lloop_bss
|
||||
|
||||
.Lenclbss:
|
||||
|
||||
bl Init_Uart /* Initialize UART */
|
||||
|
||||
|
||||
/* make sure argc and argv are valid */
|
||||
mov x0, #0
|
||||
mov x1, #0
|
||||
|
||||
bl main /* Jump to main C code */
|
||||
|
||||
|
||||
|
||||
bl _exit
|
||||
|
||||
.Lexit: /* should never get here */
|
||||
b .Lexit
|
||||
|
||||
.Lstart:
|
||||
.size _startup,.Lstart-_startup
|
178
lib/bsp/standalone/src/cortexa53/gcc/xpseudo_asm_gcc.h
Normal file
178
lib/bsp/standalone/src/cortexa53/gcc/xpseudo_asm_gcc.h
Normal file
|
@ -0,0 +1,178 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xpseudo_asm_gcc.h
|
||||
*
|
||||
* This header file contains macros for using inline assembler code. It is
|
||||
* written specifically for the GNU compiler.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/21/14 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
|
||||
#define XPSEUDO_ASM_GCC_H /* by using protection macros */
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/* necessary for pre-processor */
|
||||
#define stringify(s) tostring(s)
|
||||
#define tostring(s) #s
|
||||
|
||||
/* pseudo assembler instructions */
|
||||
#define mfcpsr() ({u32 rval; \
|
||||
asm volatile("mrs %0, DAIF" : "=r" (rval));\
|
||||
rval;\
|
||||
})
|
||||
|
||||
#define mtcpsr(v) asm ("msr DAIF, %0" : : "r" (v))
|
||||
|
||||
#define cpsiei() //__asm__ __volatile__("cpsie i\n")
|
||||
#define cpsidi() //__asm__ __volatile__("cpsid i\n")
|
||||
|
||||
#define cpsief() //__asm__ __volatile__("cpsie f\n")
|
||||
#define cpsidf() //__asm__ __volatile__("cpsid f\n")
|
||||
|
||||
|
||||
|
||||
#define mtgpr(rn, v) /*__asm__ __volatile__(\
|
||||
"mov r" stringify(rn) ", %0 \n"\
|
||||
: : "r" (v)\
|
||||
)*/
|
||||
|
||||
#define mfgpr(rn) /*({u32 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"mov %0,r" stringify(rn) "\n"\
|
||||
: "=r" (rval)\
|
||||
);\
|
||||
rval;\
|
||||
})*/
|
||||
|
||||
/* memory synchronization operations */
|
||||
|
||||
/* Instruction Synchronization Barrier */
|
||||
#define isb() asm ("isb sy")
|
||||
|
||||
/* Data Synchronization Barrier */
|
||||
#define dsb() asm("dsb sy")
|
||||
|
||||
/* Data Memory Barrier */
|
||||
#define dmb() asm("dmb sy")
|
||||
|
||||
|
||||
/* Memory Operations */
|
||||
#define ldr(adr) ({u32 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"ldr %0,[%1]"\
|
||||
: "=r" (rval) : "r" (adr)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
#define ldrb(adr) ({u8 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"ldrb %0,[%1]"\
|
||||
: "=r" (rval) : "r" (adr)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
#define str(adr, val) __asm__ __volatile__(\
|
||||
"str %0,[%1]\n"\
|
||||
: : "r" (val), "r" (adr)\
|
||||
)
|
||||
|
||||
#define strb(adr, val) __asm__ __volatile__(\
|
||||
"strb %0,[%1]\n"\
|
||||
: : "r" (val), "r" (adr)\
|
||||
)
|
||||
|
||||
/* Count leading zeroes (clz) */
|
||||
#define clz(arg) ({u8 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"clz %0,%1"\
|
||||
: "=r" (rval) : "r" (arg)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
#define mtcpdc(reg,val) asm("dc " #reg ",%0" : : "r" (val))
|
||||
#define mtcpic(reg,val) asm("ic " #reg ",%0" : : "r" (val))
|
||||
|
||||
#define mtcpicall(reg) asm("ic " #reg)
|
||||
#define mtcptlbi(reg) asm("tlbi " #reg)
|
||||
#define mtcpat(reg,val) asm("at " #reg ",%0" : : "r" (val))
|
||||
/* CP15 operations */
|
||||
#define mfcp(reg) ({u32 rval;\
|
||||
asm("mrs %0, " #reg : "=r" (rval));\
|
||||
rval;\
|
||||
})
|
||||
|
||||
#define mtcp(reg,val) asm("msr " #reg ",%0" : : "r" (val))
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
|
||||
/************************** Function Prototypes *****************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XPSEUDO_ASM_GCC_H */
|
32
lib/bsp/standalone/src/cortexa53/print.c
Normal file
32
lib/bsp/standalone/src/cortexa53/print.c
Normal file
|
@ -0,0 +1,32 @@
|
|||
/* print.c -- print a string on the output device.
|
||||
*
|
||||
* Copyright (c) 1995 Cygnus Support
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* print -- do a raw print of a string
|
||||
*/
|
||||
#include "xil_printf.h"
|
||||
|
||||
void print(const char8 *ptr)
|
||||
{
|
||||
#ifdef STDOUT_BASEADDRESS
|
||||
while (*ptr != (char8)0) {
|
||||
outbyte (*ptr);
|
||||
*ptr++;
|
||||
}
|
||||
#else
|
||||
(void)ptr;
|
||||
#endif
|
||||
}
|
59
lib/bsp/standalone/src/cortexa53/putnum.c
Normal file
59
lib/bsp/standalone/src/cortexa53/putnum.c
Normal file
|
@ -0,0 +1,59 @@
|
|||
/* putnum.c -- put a hex number on the output device.
|
||||
*
|
||||
* Copyright (c) 1995 Cygnus Support
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*/
|
||||
|
||||
/*
|
||||
* putnum -- print a 32 bit number in hex
|
||||
*/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xil_types.h"
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
extern void print (const char8 *ptr);
|
||||
void putnum(u32 num);
|
||||
|
||||
void putnum(u32 num)
|
||||
{
|
||||
char8 buf[9];
|
||||
u32 cnt;
|
||||
s32 i;
|
||||
char8 *ptr;
|
||||
u32 digit;
|
||||
for(i = 0; i<9; i++) {
|
||||
buf[i] = '0';
|
||||
}
|
||||
|
||||
ptr = buf;
|
||||
for (cnt = 7U ; cnt >= 0U ; cnt--) {
|
||||
digit = ((num >> (cnt * 4U)) & 0x0000000FU);
|
||||
|
||||
if ((digit <= 9U) && (ptr != NULL)) {
|
||||
digit += (u32)'0';
|
||||
*ptr = ((char8) digit);
|
||||
ptr += 1;
|
||||
} else if (ptr != NULL) {
|
||||
digit += ((u32)'a' - (u32)10);
|
||||
*ptr = ((char8)digit);
|
||||
ptr += 1;
|
||||
} else {
|
||||
/*Made for MisraC Compliance*/;
|
||||
}
|
||||
}
|
||||
|
||||
if(ptr != NULL) {
|
||||
*ptr = (char8) 0;
|
||||
}
|
||||
print (buf);
|
||||
}
|
95
lib/bsp/standalone/src/cortexa53/sleep.c
Normal file
95
lib/bsp/standalone/src/cortexa53/sleep.c
Normal file
|
@ -0,0 +1,95 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* @file sleep.c
|
||||
*
|
||||
* This function provides a second delay using the Global Timer register in
|
||||
* the ARM Cortex A53 MP core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "sleep.h"
|
||||
#include "xtime_l.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* This API is used to provide delays in seconds
|
||||
*
|
||||
* @param seconds requested
|
||||
*
|
||||
* @return 0 always
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
s32 sleep(u32 seconds)
|
||||
{
|
||||
XTime tEnd, tCur;
|
||||
/*write 50MHz frequency to System Time Stamp Generator Register*/
|
||||
Xil_Out32(0xFF250020U,0x02FAF080U);
|
||||
/*Enable the counter*/
|
||||
Xil_Out32(0xFF260000U,0x00000001U);
|
||||
|
||||
XTime_GetTime(&tCur);
|
||||
tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
|
||||
do
|
||||
{
|
||||
XTime_GetTime(&tCur);
|
||||
} while (tCur < tEnd);
|
||||
|
||||
/*Disable the counter*/
|
||||
Xil_Out32(0xFF260000U,0x00000000U);
|
||||
return 0;
|
||||
}
|
61
lib/bsp/standalone/src/cortexa53/sleep.h
Normal file
61
lib/bsp/standalone/src/cortexa53/sleep.h
Normal file
|
@ -0,0 +1,61 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef SLEEP_H
|
||||
#define SLEEP_H
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
s32 usleep(u32 useconds);
|
||||
s32 sleep(u32 seconds);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
173
lib/bsp/standalone/src/cortexa53/uart.c
Normal file
173
lib/bsp/standalone/src/cortexa53/uart.c
Normal file
|
@ -0,0 +1,173 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file uart.c
|
||||
*
|
||||
* This file contains APIs for configuring the UART.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xil_io.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/* Register offsets */
|
||||
#define UART_CR_OFFSET 0x00000000U
|
||||
#define UART_MR_OFFSET 0x00000004U
|
||||
#define UART_BAUDGEN_OFFSET 0x00000018U
|
||||
#define UART_BAUDDIV_OFFSET 0x00000034U
|
||||
|
||||
#define MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
|
||||
#define UART_BAUDRATE 115200U
|
||||
#define CSU_VERSION_REG 0xFFCA0044U
|
||||
|
||||
void Init_Uart(void);
|
||||
|
||||
void Init_Uart(void)
|
||||
{
|
||||
#ifdef STDOUT_BASEADDRESS
|
||||
u8 IterBAUDDIV; /* Iterator for available baud divisor values */
|
||||
u32 BRGR_Value; /* Calculated value for baud rate generator */
|
||||
u32 CalcBaudRate; /* Calculated baud rate */
|
||||
u32 BaudError; /* Diff between calculated and requested baud
|
||||
* rate */
|
||||
u32 Best_BRGR = 0U; /* Best value for baud rate generator */
|
||||
u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
|
||||
u32 Best_Error = 0xFFFFFFFFU;
|
||||
u32 PercentError;
|
||||
u32 InputClk;
|
||||
u32 BaudRate = UART_BAUDRATE;
|
||||
|
||||
/* set CD and BDIV */
|
||||
|
||||
#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
|
||||
InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
|
||||
#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
|
||||
InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
|
||||
#else
|
||||
/* STDIO is not set or axi_uart is being used for STDIO */
|
||||
return;
|
||||
#endif
|
||||
InputClk = 25000000U;
|
||||
/*
|
||||
* Determine the Baud divider. It can be 4to 254.
|
||||
* Loop through all possible combinations
|
||||
*/
|
||||
for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) {
|
||||
|
||||
/*
|
||||
* Calculate the value for BRGR register
|
||||
*/
|
||||
BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 1U));
|
||||
|
||||
/*
|
||||
* Calculate the baud rate from the BRGR value
|
||||
*/
|
||||
CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 1U));
|
||||
|
||||
/*
|
||||
* Avoid unsigned integer underflow
|
||||
*/
|
||||
if (BaudRate > CalcBaudRate) {
|
||||
BaudError = BaudRate - CalcBaudRate;
|
||||
} else {
|
||||
BaudError = CalcBaudRate - BaudRate;
|
||||
}
|
||||
|
||||
/*
|
||||
* Find the calculated baud rate closest to requested baud rate.
|
||||
*/
|
||||
if (Best_Error > BaudError) {
|
||||
|
||||
Best_BRGR = BRGR_Value;
|
||||
Best_BAUDDIV = IterBAUDDIV;
|
||||
Best_Error = BaudError;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure the best error is not too large.
|
||||
*/
|
||||
PercentError = (Best_Error * 100U) / BaudRate;
|
||||
if (((u32)MAX_BAUD_ERROR_RATE) < PercentError) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* set CD and BDIV */
|
||||
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
|
||||
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV);
|
||||
|
||||
/*
|
||||
* Veloce specific code
|
||||
*/
|
||||
if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) {
|
||||
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 2U);
|
||||
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 4U);
|
||||
}
|
||||
|
||||
/*
|
||||
* 8 data, 1 stop, 0 parity bits
|
||||
* sel_clk=uart_clk=APB clock
|
||||
*/
|
||||
Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U);
|
||||
|
||||
/* enable Tx/Rx and reset Tx/Rx data path */
|
||||
Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U);
|
||||
|
||||
return;
|
||||
#endif
|
||||
}
|
102
lib/bsp/standalone/src/cortexa53/usleep.c
Normal file
102
lib/bsp/standalone/src/cortexa53/usleep.c
Normal file
|
@ -0,0 +1,102 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file usleep.c
|
||||
*
|
||||
* This function provides a microsecond delay using the Global Timer register in
|
||||
* the ARM Cortex A53 MP core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "sleep.h"
|
||||
#include "xtime_l.h"
|
||||
#include "xparameters.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#include "xreg_cortexa53.h"
|
||||
|
||||
/* Global Timer is always clocked at half of the CPU frequency */
|
||||
#define COUNTS_PER_USECOND (COUNTS_PER_SECOND/1000000 )
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This API gives a delay in microseconds
|
||||
*
|
||||
* @param useconds requested
|
||||
*
|
||||
* @return 0 if the delay can be achieved, -1 if the requested delay
|
||||
* is out of range
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
s32 usleep(u32 useconds)
|
||||
{
|
||||
XTime tEnd, tCur;
|
||||
/*write 50MHz frequency to System Time Stamp Generator Register*/
|
||||
Xil_Out32(0xFF250020U,0x02FAF080U);
|
||||
/*Enable the counter*/
|
||||
Xil_Out32(0xFF260000U,0x00000001U);
|
||||
|
||||
XTime_GetTime(&tCur);
|
||||
tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
|
||||
do
|
||||
{
|
||||
XTime_GetTime(&tCur);
|
||||
} while (tCur < tEnd);
|
||||
|
||||
/*Disable the counter*/
|
||||
Xil_Out32(0xFF260000U,0x00000000U);
|
||||
return 0;
|
||||
}
|
160
lib/bsp/standalone/src/cortexa53/vectors.c
Normal file
160
lib/bsp/standalone/src/cortexa53/vectors.c
Normal file
|
@ -0,0 +1,160 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file vectors.c
|
||||
*
|
||||
* This file contains the C level vectors for the ARM Cortex A53 core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_exception.h"
|
||||
#include "vectors.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
typedef struct {
|
||||
Xil_ExceptionHandler Handler;
|
||||
void *Data;
|
||||
} XExc_VectorTableEntry;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
extern XExc_VectorTableEntry XExc_VectorTable[];
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This is the C level wrapper for the FIQ interrupt called from the vectors.s
|
||||
* file.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void FIQInterrupt(void)
|
||||
{
|
||||
XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
|
||||
XIL_EXCEPTION_ID_FIQ_INT].Data);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This is the C level wrapper for the IRQ interrupt called from the vectors.s
|
||||
* file.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void IRQInterrupt(void)
|
||||
{
|
||||
XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
|
||||
XIL_EXCEPTION_ID_IRQ_INT].Data);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
|
||||
* file.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void SynchronousInterrupt(void)
|
||||
{
|
||||
XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
|
||||
XIL_EXCEPTION_ID_SYNC_INT].Data);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This is the C level wrapper for the SError Interrupt called from the
|
||||
* vectors.s file.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void SErrorInterrupt(void)
|
||||
{
|
||||
XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
|
||||
XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
|
||||
}
|
92
lib/bsp/standalone/src/cortexa53/vectors.h
Normal file
92
lib/bsp/standalone/src/cortexa53/vectors.h
Normal file
|
@ -0,0 +1,92 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file vectors.h
|
||||
*
|
||||
* This file contains the C level vector prototypes for the ARM Cortex A53 core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _VECTORS_H_
|
||||
#define _VECTORS_H_
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
void FIQInterrupt(void);
|
||||
void IRQInterrupt(void);
|
||||
void SynchronousInterrupt(void);
|
||||
void SErrorInterrupt(void);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* protection macro */
|
659
lib/bsp/standalone/src/cortexa53/xil_cache.c
Normal file
659
lib/bsp/standalone/src/cortexa53/xil_cache.c
Normal file
|
@ -0,0 +1,659 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_cache.c
|
||||
*
|
||||
* Contains required functions for the ARM cache functionality. Cache APIs are
|
||||
* yet to be implemented. They are left blank to avoid any compilation error
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_cache.h"
|
||||
#include "xil_io.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#include "xparameters.h"
|
||||
#include "xreg_cortexa53.h"
|
||||
#include "xil_exception.h"
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Enable the Data cache.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void Xil_DCacheEnable(void)
|
||||
{
|
||||
u32 CtrlReg;
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
/* enable caches only if they are disabled */
|
||||
if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){
|
||||
|
||||
/* invalidate the Data cache */
|
||||
Xil_DCacheInvalidate();
|
||||
|
||||
CtrlReg |= XREG_CONTROL_DCACHE_BIT;
|
||||
|
||||
/* enable the Data cache */
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Disable the Data cache.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_DCacheDisable(void)
|
||||
{
|
||||
u32 CtrlReg;
|
||||
/* clean and invalidate the Data cache */
|
||||
Xil_DCacheFlush();
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
|
||||
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
|
||||
/* disable the Data cache */
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* invalidate the Data cache.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_DCacheInvalidate(void)
|
||||
{
|
||||
register u32 CsidReg, C7Reg;
|
||||
u32 LineSize, NumWays;
|
||||
u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
|
||||
u32 currmask;
|
||||
|
||||
currmask = mfcpsr();
|
||||
mtcpsr(currmask | IRQ_FIQ_MASK);
|
||||
|
||||
|
||||
/* Number of level of cache*/
|
||||
NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
|
||||
|
||||
CacheLevel=0U;
|
||||
/* Select cache level 0 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,CacheLevel);
|
||||
isb();
|
||||
|
||||
CsidReg = mfcp(CCSIDR_EL1);
|
||||
|
||||
/* Get the cacheline size, way size, index size from csidr */
|
||||
LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
|
||||
|
||||
/* Number of Ways */
|
||||
NumWays = (CsidReg & 0x00001FFFU) >> 3U;
|
||||
NumWays += 0X00000001U;
|
||||
|
||||
/*Number of Set*/
|
||||
NumSet = (CsidReg >> 13U) & 0x00007FFFU;
|
||||
NumSet += 0X00000001U;
|
||||
|
||||
WayAdjust = clz(NumWays) - (u32)0x0000001FU;
|
||||
|
||||
Way = 0U;
|
||||
Set = 0U;
|
||||
|
||||
/* Invalidate all the cachelines */
|
||||
for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
|
||||
for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
|
||||
C7Reg = Way | Set | CacheLevel;
|
||||
mtcpdc(ISW,C7Reg);
|
||||
Set += (0x00000001U << LineSize);
|
||||
}
|
||||
Set = 0U;
|
||||
Way += (0x00000001U << WayAdjust);
|
||||
}
|
||||
|
||||
/* Wait for invalidate to complete */
|
||||
dsb();
|
||||
|
||||
/* Select cache level 1 and D cache in CSSR */
|
||||
CacheLevel += (0x00000001U<<1U) ;
|
||||
mtcp(CSSELR_EL1,CacheLevel);
|
||||
isb();
|
||||
|
||||
CsidReg = mfcp(CCSIDR_EL1);
|
||||
|
||||
/* Get the cacheline size, way size, index size from csidr */
|
||||
LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
|
||||
|
||||
/* Number of Ways */
|
||||
NumWays = (CsidReg & 0x00001FFFU) >> 3U;
|
||||
NumWays += 0x00000001U;
|
||||
|
||||
/* Number of Sets */
|
||||
NumSet = (CsidReg >> 13U) & 0x00007FFFU;
|
||||
NumSet += 0x00000001U;
|
||||
|
||||
WayAdjust = clz(NumWays) - (u32)0x0000001FU;
|
||||
|
||||
Way = 0U;
|
||||
Set = 0U;
|
||||
|
||||
/* Invalidate all the cachelines */
|
||||
for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
|
||||
for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
|
||||
C7Reg = Way | Set | CacheLevel;
|
||||
mtcpdc(ISW,C7Reg);
|
||||
Set += (0x00000001U << LineSize);
|
||||
}
|
||||
Set = 0U;
|
||||
Way += (0x00000001U << WayAdjust);
|
||||
}
|
||||
/* Wait for invalidate to complete */
|
||||
dsb();
|
||||
|
||||
mtcpsr(currmask);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Invalidate a Data cache line. If the byte specified by the address (adr)
|
||||
* is cached by the Data cache, the cacheline containing that byte is
|
||||
* invalidated. If the cacheline is modified (dirty), the modified contents
|
||||
* are written to system memory before the line is invalidated.
|
||||
*
|
||||
* @param Address to be flushed.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The bottom 6 bits are set to 0, forced by architecture.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_DCacheInvalidateLine(INTPTR adr)
|
||||
{
|
||||
|
||||
u32 currmask;
|
||||
currmask = mfcpsr();
|
||||
mtcpsr(currmask | IRQ_FIQ_MASK);
|
||||
|
||||
/* Select cache level 0 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,0x0);
|
||||
mtcpdc(IVAC,(adr & (~0x3F)));
|
||||
/* Wait for invalidate to complete */
|
||||
dsb();
|
||||
/* Select cache level 1 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,0x2);
|
||||
mtcpdc(IVAC,(adr & (~0x3F)));
|
||||
/* Wait for invalidate to complete */
|
||||
dsb();
|
||||
mtcpsr(currmask);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Invalidate the Data cache for the given address range.
|
||||
* If the bytes specified by the address (adr) are cached by the Data cache,
|
||||
* the cacheline containing that byte is invalidated. If the cacheline
|
||||
* is modified (dirty), the modified contents are written to system memory
|
||||
* before the line is invalidated.
|
||||
*
|
||||
* @param Start address of range to be invalidated.
|
||||
* @param Length of range to be invalidated in bytes.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
|
||||
{
|
||||
const u32 cacheline = 64U;
|
||||
u32 end;
|
||||
u32 tempadr = adr;
|
||||
u32 tempend;
|
||||
u32 currmask;
|
||||
currmask = mfcpsr();
|
||||
mtcpsr(currmask | IRQ_FIQ_MASK);
|
||||
if (len != 0U) {
|
||||
end = tempadr + len;
|
||||
tempend = end;
|
||||
|
||||
if ((tempadr & (cacheline-1U)) != 0U) {
|
||||
tempadr &= (~(cacheline - 1U));
|
||||
Xil_DCacheFlushLine(tempadr);
|
||||
tempadr += cacheline;
|
||||
}
|
||||
if ((tempend & (cacheline-1U)) != 0U) {
|
||||
tempend &= (~(cacheline - 1U));
|
||||
Xil_DCacheFlushLine(tempend);
|
||||
}
|
||||
|
||||
while (tempadr < tempend) {
|
||||
/* Select cache level 0 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,0x0);
|
||||
/* Invalidate Data cache line */
|
||||
mtcpdc(IVAC,(tempadr & (~0x3F)));
|
||||
/* Wait for invalidate to complete */
|
||||
dsb();
|
||||
/* Select cache level 0 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,0x2);
|
||||
/* Invalidate Data cache line */
|
||||
mtcpdc(IVAC,(tempadr & (~0x3F)));
|
||||
/* Wait for invalidate to complete */
|
||||
dsb();
|
||||
tempadr += cacheline;
|
||||
}
|
||||
}
|
||||
mtcpsr(currmask);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Flush the Data cache.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_DCacheFlush(void)
|
||||
{
|
||||
register u32 CsidReg, C7Reg;
|
||||
u32 LineSize, NumWays;
|
||||
u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
|
||||
u32 currmask;
|
||||
|
||||
currmask = mfcpsr();
|
||||
mtcpsr(currmask | IRQ_FIQ_MASK);
|
||||
|
||||
|
||||
/* Number of level of cache*/
|
||||
NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
|
||||
|
||||
CacheLevel = 0U;
|
||||
/* Select cache level 0 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,CacheLevel);
|
||||
isb();
|
||||
|
||||
CsidReg = mfcp(CCSIDR_EL1);
|
||||
|
||||
/* Get the cacheline size, way size, index size from csidr */
|
||||
LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
|
||||
|
||||
/* Number of Ways */
|
||||
NumWays = (CsidReg & 0x00001FFFU) >> 3U;
|
||||
NumWays += 0x00000001U;
|
||||
|
||||
/*Number of Set*/
|
||||
NumSet = (CsidReg >> 13U) & 0x00007FFFU;
|
||||
NumSet += 0x00000001U;
|
||||
|
||||
WayAdjust = clz(NumWays) - (u32)0x0000001FU;
|
||||
|
||||
Way = 0U;
|
||||
Set = 0U;
|
||||
|
||||
/* Flush all the cachelines */
|
||||
for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
|
||||
for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
|
||||
C7Reg = Way | Set | CacheLevel;
|
||||
mtcpdc(CISW,C7Reg);
|
||||
Set += (0x00000001U << LineSize);
|
||||
}
|
||||
Set = 0U;
|
||||
Way += (0x00000001U << WayAdjust);
|
||||
}
|
||||
|
||||
/* Wait for Flush to complete */
|
||||
dsb();
|
||||
|
||||
/* Select cache level 1 and D cache in CSSR */
|
||||
CacheLevel += (0x00000001U << 1U);
|
||||
mtcp(CSSELR_EL1,CacheLevel);
|
||||
isb();
|
||||
|
||||
CsidReg = mfcp(CCSIDR_EL1);
|
||||
|
||||
/* Get the cacheline size, way size, index size from csidr */
|
||||
LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
|
||||
|
||||
/* Number of Ways */
|
||||
NumWays = (CsidReg & 0x00001FFFU) >> 3U;
|
||||
NumWays += 0x00000001U;
|
||||
|
||||
/* Number of Sets */
|
||||
NumSet = (CsidReg >> 13U) & 0x00007FFFU;
|
||||
NumSet += 0x00000001U;
|
||||
|
||||
WayAdjust=clz(NumWays) - (u32)0x0000001FU;
|
||||
|
||||
Way = 0U;
|
||||
Set = 0U;
|
||||
|
||||
/* Flush all the cachelines */
|
||||
for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
|
||||
for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
|
||||
C7Reg = Way | Set | CacheLevel;
|
||||
mtcpdc(CISW,C7Reg);
|
||||
Set += (0x00000001U << LineSize);
|
||||
}
|
||||
Set=0U;
|
||||
Way += (0x00000001U<<WayAdjust);
|
||||
}
|
||||
/* Wait for Flush to complete */
|
||||
dsb();
|
||||
|
||||
mtcpsr(currmask);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Flush a Data cache line. If the byte specified by the address (adr)
|
||||
* is cached by the Data cache, the cacheline containing that byte is
|
||||
* invalidated. If the cacheline is modified (dirty), the entire
|
||||
* contents of the cacheline are written to system memory before the
|
||||
* line is invalidated.
|
||||
*
|
||||
* @param Address to be flushed.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The bottom 6 bits are set to 0, forced by architecture.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_DCacheFlushLine(INTPTR adr)
|
||||
{
|
||||
u32 currmask;
|
||||
currmask = mfcpsr();
|
||||
mtcpsr(currmask | IRQ_FIQ_MASK);
|
||||
/* Select cache level 0 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,0x0);
|
||||
mtcpdc(CIVAC,(adr & (~0x3F)));
|
||||
/* Wait for flush to complete */
|
||||
dsb();
|
||||
/* Select cache level 1 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,0x2);
|
||||
mtcpdc(CIVAC,(adr & (~0x3F)));
|
||||
/* Wait for flush to complete */
|
||||
dsb();
|
||||
mtcpsr(currmask);
|
||||
}
|
||||
/****************************************************************************
|
||||
* Flush the Data cache for the given address range.
|
||||
* If the bytes specified by the address (adr) are cached by the Data cache,
|
||||
* the cacheline containing that byte is invalidated. If the cacheline
|
||||
* is modified (dirty), the written to system memory first before the
|
||||
* before the line is invalidated.
|
||||
*
|
||||
* @param Start address of range to be flushed.
|
||||
* @param Length of range to be flushed in bytes.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void Xil_DCacheFlushRange(INTPTR adr, u32 len)
|
||||
{
|
||||
const u32 cacheline = 64U;
|
||||
u32 end;
|
||||
u32 tempadr = adr;
|
||||
u32 tempend;
|
||||
u32 currmask;
|
||||
currmask = mfcpsr();
|
||||
mtcpsr(currmask | IRQ_FIQ_MASK);
|
||||
if (len != 0x00000000U) {
|
||||
end = tempadr + len;
|
||||
tempend = end;
|
||||
if (tempadr & (cacheline - 0x00000001U) != 0x00000000U) {
|
||||
tempadr &= ~(cacheline - 0x00000001U);
|
||||
Xil_DCacheFlushLine(tempadr);
|
||||
tempadr += cacheline;
|
||||
}
|
||||
if (tempend & (cacheline-0x00000001U) != 0x00000000U) {
|
||||
tempend &= ~(cacheline - 0x00000001U);
|
||||
Xil_DCacheFlushLine(tempend);
|
||||
}
|
||||
|
||||
while (tempadr < tempend) {
|
||||
/* Select cache level 0 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,0x0);
|
||||
/* Flush Data cache line */
|
||||
mtcpdc(CIVAC,(tempadr & (~0x3F)));
|
||||
/* Wait for flush to complete */
|
||||
dsb();
|
||||
/* Select cache level 1 and D cache in CSSR */
|
||||
mtcp(CSSELR_EL1,0x2);
|
||||
/* Flush Data cache line */
|
||||
mtcpdc(CIVAC,(tempadr & (~0x3F)));
|
||||
/* Wait for flush to complete */
|
||||
dsb();
|
||||
tempadr += cacheline;
|
||||
}
|
||||
}
|
||||
|
||||
mtcpsr(currmask);
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Enable the instruction cache.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
void Xil_ICacheEnable(void)
|
||||
{
|
||||
|
||||
u32 CtrlReg;
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
/* enable caches only if they are disabled */
|
||||
if((CtrlReg & XREG_CONTROL_ICACHE_BIT)==0x00000000U){
|
||||
/* invalidate the instruction cache */
|
||||
Xil_ICacheInvalidate();
|
||||
|
||||
CtrlReg |= XREG_CONTROL_ICACHE_BIT;
|
||||
/* enable the instruction cache */
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Disable the instruction cache.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_ICacheDisable(void)
|
||||
{
|
||||
u32 CtrlReg;
|
||||
CtrlReg = mfcp(SCTLR_EL3);
|
||||
/* invalidate the instruction cache */
|
||||
Xil_ICacheInvalidate();
|
||||
CtrlReg &= ~(XREG_CONTROL_ICACHE_BIT);
|
||||
/* disable the instruction cache */
|
||||
mtcp(SCTLR_EL3,CtrlReg);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Invalidate the entire instruction cache.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_ICacheInvalidate(void)
|
||||
{
|
||||
unsigned int currmask;
|
||||
currmask = mfcpsr();
|
||||
mtcpsr(currmask | IRQ_FIQ_MASK);
|
||||
mtcp(CSSELR_EL1,0x1);
|
||||
dsb();
|
||||
/* invalidate the instruction cache */
|
||||
mtcpicall(IALLU);
|
||||
/* Wait for invalidate to complete */
|
||||
dsb();
|
||||
mtcpsr(currmask);
|
||||
}
|
||||
/****************************************************************************
|
||||
*
|
||||
* Invalidate an instruction cache line. If the instruction specified by the
|
||||
* parameter adr is cached by the instruction cache, the cacheline containing
|
||||
* that instruction is invalidated.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The bottom 6 bits are set to 0, forced by architecture.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void Xil_ICacheInvalidateLine(INTPTR adr)
|
||||
{
|
||||
u32 currmask;
|
||||
currmask = mfcpsr();
|
||||
mtcpsr(currmask | IRQ_FIQ_MASK);
|
||||
|
||||
mtcp(CSSELR_EL1,0x1);
|
||||
/*Invalidate I Cache line*/
|
||||
mtcpic(IVAU,adr & (~0x3F));
|
||||
/* Wait for invalidate to complete */
|
||||
dsb();
|
||||
mtcpsr(currmask);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Invalidate the instruction cache for the given address range.
|
||||
* If the bytes specified by the address (adr) are cached by the Data cache,
|
||||
* the cacheline containing that byte is invalidated. If the cacheline
|
||||
* is modified (dirty), the modified contents are lost and are NOT
|
||||
* written to system memory before the line is invalidated.
|
||||
*
|
||||
* @param Start address of range to be invalidated.
|
||||
* @param Length of range to be invalidated in bytes.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
|
||||
{
|
||||
const u32 cacheline = 64U;
|
||||
u32 end;
|
||||
u32 tempadr = adr;
|
||||
u32 tempend;
|
||||
u32 currmask;
|
||||
currmask = mfcpsr();
|
||||
mtcpsr(currmask | IRQ_FIQ_MASK);
|
||||
|
||||
if (len != 0x00000000U) {
|
||||
end = tempadr + len;
|
||||
tempend = end;
|
||||
tempadr &= ~(cacheline - 0x00000001U);
|
||||
|
||||
/* Select cache Level 0 I-cache in CSSR */
|
||||
mtcp(CSSELR_EL1,0x1);
|
||||
while (tempadr < tempend) {
|
||||
/*Invalidate I Cache line*/
|
||||
mtcpic(IVAU,adr & (~0x3F));
|
||||
|
||||
tempadr += cacheline;
|
||||
}
|
||||
}
|
||||
/* Wait for invalidate to complete */
|
||||
dsb();
|
||||
mtcpsr(currmask);
|
||||
}
|
86
lib/bsp/standalone/src/cortexa53/xil_cache.h
Normal file
86
lib/bsp/standalone/src/cortexa53/xil_cache.h
Normal file
|
@ -0,0 +1,86 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_cache.h
|
||||
*
|
||||
* Contains required functions for the ARM cache functionality
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XIL_CACHE_H
|
||||
#define XIL_CACHE_H
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void Xil_DCacheEnable(void);
|
||||
void Xil_DCacheDisable(void);
|
||||
void Xil_DCacheInvalidate(void);
|
||||
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
|
||||
void Xil_DCacheInvalidateLine(INTPTR adr);
|
||||
void Xil_DCacheFlush(void);
|
||||
void Xil_DCacheFlushRange(INTPTR adr, u32 len);
|
||||
void Xil_DCacheFlushLine(INTPTR adr);
|
||||
|
||||
void Xil_ICacheEnable(void);
|
||||
void Xil_ICacheDisable(void);
|
||||
void Xil_ICacheInvalidate(void);
|
||||
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
|
||||
void Xil_ICacheInvalidateLine(INTPTR adr);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
225
lib/bsp/standalone/src/cortexa53/xil_exception.c
Normal file
225
lib/bsp/standalone/src/cortexa53/xil_exception.c
Normal file
|
@ -0,0 +1,225 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_exception.c
|
||||
*
|
||||
* This file contains low-level driver functions for the Cortex A53 exception
|
||||
* Handler.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xil_exception.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#include "xdebug.h"
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
typedef struct {
|
||||
Xil_ExceptionHandler Handler;
|
||||
void *Data;
|
||||
} XExc_VectorTableEntry;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/************************** Function Prototypes *****************************/
|
||||
|
||||
static void Xil_ExceptionNullHandler(void *Data);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
/*
|
||||
* Exception vector table to store handlers for each exception vector.
|
||||
*/
|
||||
XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
|
||||
{
|
||||
{Xil_ExceptionNullHandler, NULL},
|
||||
{Xil_SyncAbortHandler, NULL},
|
||||
{Xil_ExceptionNullHandler, NULL},
|
||||
{Xil_ExceptionNullHandler, NULL},
|
||||
{Xil_SErrorAbortHandler, NULL},
|
||||
|
||||
};
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function is a stub Handler that is the default Handler that gets called
|
||||
* if the application has not setup a Handler for a specific exception. The
|
||||
* function interface has to match the interface specified for a Handler even
|
||||
* though none of the arguments are used.
|
||||
*
|
||||
* @param Data is unused by this function.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
static void Xil_ExceptionNullHandler(void *Data)
|
||||
{
|
||||
(void *)Data;
|
||||
DieLoop: goto DieLoop;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* The function is a common API used to initialize exception handlers across all
|
||||
* processors supported. For ARM CortexA53, the exception handlers are being
|
||||
* initialized statically and hence this function does not do anything.
|
||||
*
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
void Xil_ExceptionInit(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Makes the connection between the Id of the exception source and the
|
||||
* associated Handler that is to run when the exception is recognized. The
|
||||
* argument provided in this call as the Data is used as the argument
|
||||
* for the Handler when it is called.
|
||||
*
|
||||
* @param exception_id contains the ID of the exception source and should
|
||||
* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
|
||||
See xil_exception_l.h for further information.
|
||||
* @param Handler to the Handler for that exception.
|
||||
* @param Data is a reference to Data that will be passed to the
|
||||
* Handler when it gets called.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_ExceptionRegisterHandler(u32 Exception_id,
|
||||
Xil_ExceptionHandler Handler,
|
||||
void *Data)
|
||||
{
|
||||
XExc_VectorTable[Exception_id].Handler = Handler;
|
||||
XExc_VectorTable[Exception_id].Data = Data;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Removes the Handler for a specific exception Id. The stub Handler is then
|
||||
* registered for this exception Id.
|
||||
*
|
||||
* @param exception_id contains the ID of the exception source and should
|
||||
* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
|
||||
* See xil_exception_l.h for further information.
|
||||
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_ExceptionRemoveHandler(u32 Exception_id)
|
||||
{
|
||||
Xil_ExceptionRegisterHandler(Exception_id,
|
||||
Xil_ExceptionNullHandler,
|
||||
NULL);
|
||||
}
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Default Synchronous abort handler which prints a debug message on console if
|
||||
* Debug flag is enabled
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void Xil_SyncAbortHandler(void *CallBackRef){
|
||||
xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
|
||||
while(1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Default SError abort handler which prints a debug message on console if
|
||||
* Debug flag is enabled
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void Xil_SErrorAbortHandler(void *CallBackRef){
|
||||
xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
|
||||
while(1) {
|
||||
;
|
||||
}
|
||||
}
|
179
lib/bsp/standalone/src/cortexa53/xil_exception.h
Normal file
179
lib/bsp/standalone/src/cortexa53/xil_exception.h
Normal file
|
@ -0,0 +1,179 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_exception.h
|
||||
*
|
||||
* This header file contains ARM Cortex A53 specific exception related APIs.
|
||||
* For exception related functions that can be used across all Xilinx supported
|
||||
* processors, please use xil_exception.h.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
|
||||
#define XIL_EXCEPTION_H /* by using protection macros */
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xpseudo_asm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
|
||||
#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
|
||||
#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
|
||||
|
||||
#define XIL_EXCEPTION_ID_FIRST 0U
|
||||
#define XIL_EXCEPTION_ID_SYNC_INT 1U
|
||||
#define XIL_EXCEPTION_ID_IRQ_INT 2U
|
||||
#define XIL_EXCEPTION_ID_FIQ_INT 3U
|
||||
#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
|
||||
#define XIL_EXCEPTION_ID_LAST 5U
|
||||
|
||||
/*
|
||||
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
|
||||
*/
|
||||
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
/**
|
||||
* This typedef is the exception handler function.
|
||||
*/
|
||||
typedef void (*Xil_ExceptionHandler)(void *data);
|
||||
typedef void (*Xil_InterruptHandler)(void *data);
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Enable Exceptions.
|
||||
*
|
||||
* @param Mask for exceptions to be enabled.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note If bit is 0, exception is enabled.
|
||||
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#define Xil_ExceptionEnableMask(Mask) \
|
||||
mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Enable the IRQ exception.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_ExceptionEnable() \
|
||||
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Disable Exceptions.
|
||||
*
|
||||
* @param Mask for exceptions to be enabled.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note If bit is 1, exception is disabled.
|
||||
* C-Style signature: Xil_ExceptionDisableMask(Mask)
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#define Xil_ExceptionDisableMask(Mask) \
|
||||
mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Disable the IRQ exception.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_ExceptionDisable() \
|
||||
Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
|
||||
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
|
||||
/************************** Function Prototypes *****************************/
|
||||
|
||||
extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
|
||||
Xil_ExceptionHandler Handler,
|
||||
void *Data);
|
||||
|
||||
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
|
||||
|
||||
extern void Xil_ExceptionInit(void);
|
||||
|
||||
void Xil_SyncAbortHandler(void *CallBackRef);
|
||||
|
||||
void Xil_SErrorAbortHandler(void *CallBackRef);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XIL_EXCEPTION_H */
|
392
lib/bsp/standalone/src/cortexa53/xil_io.c
Normal file
392
lib/bsp/standalone/src/cortexa53/xil_io.c
Normal file
|
@ -0,0 +1,392 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_io.c
|
||||
*
|
||||
* Contains I/O functions for memory-mapped or non-memory-mapped I/O
|
||||
* architectures. These functions encapsulate Cortex A53 architecture-specific
|
||||
* I/O requirements.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* This file contains architecture-dependent code.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xil_io.h"
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#include "xreg_cortexa53.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for an 8-bit memory location by reading from the
|
||||
* specified address and returning the Value read from that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u8 Xil_In8(INTPTR Addr)
|
||||
{
|
||||
return *(volatile u8 *) Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for a 16-bit memory location by reading from the
|
||||
* specified address and returning the Value read from that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u16 Xil_In16(INTPTR Addr)
|
||||
{
|
||||
return *(volatile u16 *) Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for a 32-bit memory location by reading from the
|
||||
* specified address and returning the Value read from that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 Xil_In32(INTPTR Addr)
|
||||
{
|
||||
return *(volatile u32 *) Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for an 8-bit memory location by writing the
|
||||
* specified Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out8(INTPTR Addr, u8 Value)
|
||||
{
|
||||
u8 *LocalAddr = (u8 *)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for a 16-bit memory location by writing the
|
||||
* specified Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out16(INTPTR Addr, u16 Value)
|
||||
{
|
||||
u16 *LocalAddr = (u16 *)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for a 32-bit memory location by writing the
|
||||
* specified Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out32(INTPTR Addr, u32 Value)
|
||||
{
|
||||
u32 *LocalAddr = (u32 *)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for a 64-bit memory location by writing the
|
||||
* specified Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out64(INTPTR Addr, u64 Value)
|
||||
{
|
||||
u64 *LocalAddr = (u64 *)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for a 64-bit memory location by reading the
|
||||
* specified Value to the the specified address.
|
||||
*
|
||||
* @param OutAddress contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u64 Xil_In64(INTPTR Addr)
|
||||
{
|
||||
return *(volatile u64 *) Addr;
|
||||
}
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for a 16-bit memory location by reading from the
|
||||
* specified address and returning the byte-swapped Value read from that
|
||||
* address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The byte-swapped Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u16 Xil_In16BE(INTPTR Addr)
|
||||
{
|
||||
u16 temp;
|
||||
u16 result;
|
||||
|
||||
temp = Xil_In16(Addr);
|
||||
|
||||
result = Xil_EndianSwap16(temp);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for a 32-bit memory location by reading from the
|
||||
* specified address and returning the byte-swapped Value read from that
|
||||
* address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The byte-swapped Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 Xil_In32BE(INTPTR Addr)
|
||||
{
|
||||
u32 temp;
|
||||
u32 result;
|
||||
|
||||
temp = Xil_In32(Addr);
|
||||
|
||||
result = Xil_EndianSwap32(temp);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for a 16-bit memory location by writing the
|
||||
* specified Value to the the specified address. The Value is byte-swapped
|
||||
* before being written.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out16BE(INTPTR Addr, u16 Value)
|
||||
{
|
||||
u16 temp;
|
||||
|
||||
temp = Xil_EndianSwap16(Value);
|
||||
|
||||
Xil_Out16(Addr, temp);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for a 32-bit memory location by writing the
|
||||
* specified Value to the the specified address. The Value is byte-swapped
|
||||
* before being written.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out32BE(INTPTR Addr, u32 Value)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
temp = Xil_EndianSwap32(Value);
|
||||
|
||||
Xil_Out32(Addr, temp);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a 16-bit endian converion.
|
||||
*
|
||||
* @param Data contains the value to be converted.
|
||||
*
|
||||
* @return converted value.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u16 Xil_EndianSwap16(u16 Data)
|
||||
{
|
||||
return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a 32-bit endian converion.
|
||||
*
|
||||
* @param Data contains the value to be converted.
|
||||
*
|
||||
* @return converted value.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 Xil_EndianSwap32(u32 Data)
|
||||
{
|
||||
u16 LoWord;
|
||||
u16 HiWord;
|
||||
|
||||
/* get each of the half words from the 32 bit word */
|
||||
|
||||
LoWord = (u16) (Data & 0x0000FFFFU);
|
||||
HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
|
||||
|
||||
/* byte swap each of the 16 bit half words */
|
||||
|
||||
LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
|
||||
HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
|
||||
|
||||
/* swap the half words before returning the value */
|
||||
|
||||
return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
|
||||
}
|
256
lib/bsp/standalone/src/cortexa53/xil_io.h
Normal file
256
lib/bsp/standalone/src/cortexa53/xil_io.h
Normal file
|
@ -0,0 +1,256 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_io.h
|
||||
*
|
||||
* This file contains the interface for the general IO component, which
|
||||
* encapsulates the Input/Output functions for processors that do not
|
||||
* require any special I/O handling.
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_IO_H /* prevent circular inclusions */
|
||||
#define XIL_IO_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#include "xil_printf.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
#if defined __GNUC__
|
||||
# define SYNCHRONIZE_IO dmb()
|
||||
# define INST_SYNC isb()
|
||||
# define DATA_SYNC dsb()
|
||||
#else
|
||||
# define SYNCHRONIZE_IO
|
||||
# define INST_SYNC
|
||||
# define DATA_SYNC
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform an big-endian input operation for a 16-bit memory location
|
||||
* by reading from the specified address and returning the Value read from
|
||||
* that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation at.
|
||||
*
|
||||
* @return The Value read from the specified input address with the
|
||||
* proper endianness. The return Value has the same endianness
|
||||
* as that of the processor, i.e. if the processor is
|
||||
* little-engian, the return Value is the byte-swapped Value read
|
||||
* from the address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_In16LE(Addr) Xil_In16((Addr))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a big-endian input operation for a 32-bit memory location
|
||||
* by reading from the specified address and returning the Value read from
|
||||
* that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation at.
|
||||
*
|
||||
* @return The Value read from the specified input address with the
|
||||
* proper endianness. The return Value has the same endianness
|
||||
* as that of the processor, i.e. if the processor is
|
||||
* little-engian, the return Value is the byte-swapped Value read
|
||||
* from the address.
|
||||
*
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_In32LE(Addr) Xil_In32((Addr))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a big-endian output operation for a 16-bit memory location
|
||||
* by writing the specified Value to the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
* The Value has the same endianness as that of the processor.
|
||||
* If the processor is little-endian, the byte-swapped Value is
|
||||
* written to the address.
|
||||
*
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a big-endian output operation for a 32-bit memory location
|
||||
* by writing the specified Value to the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
* The Value has the same endianness as that of the processor.
|
||||
* If the processor is little-endian, the byte-swapped Value is
|
||||
* written to the address.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Convert a 32-bit number from host byte order to network byte order.
|
||||
*
|
||||
* @param Data the 32-bit number to be converted.
|
||||
*
|
||||
* @return The converted 32-bit number in network byte order.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Convert a 16-bit number from host byte order to network byte order.
|
||||
*
|
||||
* @param Data the 16-bit number to be converted.
|
||||
*
|
||||
* @return The converted 16-bit number in network byte order.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Htons(Data) Xil_EndianSwap16((Data))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Convert a 32-bit number from network byte order to host byte order.
|
||||
*
|
||||
* @param Data the 32-bit number to be converted.
|
||||
*
|
||||
* @return The converted 32-bit number in host byte order.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Convert a 16-bit number from network byte order to host byte order.
|
||||
*
|
||||
* @param Data the 16-bit number to be converted.
|
||||
*
|
||||
* @return The converted 16-bit number in host byte order.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/* The following functions allow the software to be transportable across
|
||||
* processors which may use memory mapped I/O or I/O which is mapped into a
|
||||
* seperate address space.
|
||||
*/
|
||||
u8 Xil_In8(INTPTR Addr);
|
||||
u16 Xil_In16(INTPTR Addr);
|
||||
u32 Xil_In32(INTPTR Addr);
|
||||
u64 Xil_In64(INTPTR Addr);
|
||||
|
||||
void Xil_Out8(INTPTR Addr, u8 Value);
|
||||
void Xil_Out16(INTPTR Addr, u16 Value);
|
||||
void Xil_Out32(INTPTR Addr, u32 Value);
|
||||
void Xil_Out64(INTPTR Addr, u64 Value);
|
||||
|
||||
|
||||
u16 Xil_In16BE(INTPTR Addr);
|
||||
u32 Xil_In32BE(INTPTR Addr);
|
||||
void Xil_Out16BE(INTPTR Addr, u16 Value);
|
||||
void Xil_Out32BE(INTPTR Addr, u32 Value);
|
||||
|
||||
u16 Xil_EndianSwap16(u16 Data);
|
||||
u32 Xil_EndianSwap32(u32 Data);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
171
lib/bsp/standalone/src/cortexa53/xil_mmu.c
Normal file
171
lib/bsp/standalone/src/cortexa53/xil_mmu.c
Normal file
|
@ -0,0 +1,171 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xil_mmu.c
|
||||
*
|
||||
* This file provides APIs for enabling/disabling MMU and setting the memory
|
||||
* attributes for sections, in the MMU translation table.
|
||||
* MMU APIs are yet to be implemented. They are left blank to avoid any
|
||||
* compilation error
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_cache.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#include "xil_types.h"
|
||||
#include "xil_mmu.h"
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
extern INTPTR MMUTableL1;
|
||||
extern INTPTR MMUTableL2;
|
||||
/************************** Function Prototypes ******************************/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Set the memory attributes for a section, in the translation table.
|
||||
*
|
||||
* @param addr is the address for which attributes are to be set.
|
||||
* @param attrib specifies the attributes for that memory region.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The MMU and D-cache need not be disabled before changing an
|
||||
* translation table attribute.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib)
|
||||
{
|
||||
INTPTR *ptr;
|
||||
INTPTR section;
|
||||
/* if region is less than 4GB MMUTable level 2 need to be modified */
|
||||
if(Addr<0x100000000){
|
||||
section = Addr / 0x00200000U;
|
||||
ptr = &MMUTableL2 + section;
|
||||
*ptr = (Addr & (~0x001FFFFFU)) | attrib;
|
||||
}
|
||||
/* if region is greater than 4GB MMUTable level 1 need to be modified */
|
||||
else{
|
||||
section = Addr / 0x40000000U;
|
||||
ptr = &MMUTableL1 + section;
|
||||
*ptr = (Addr & (~0x3FFFFFFFU)) | attrib;
|
||||
}
|
||||
|
||||
Xil_DCacheFlush();
|
||||
mtcptlbi(ALLE3);
|
||||
|
||||
dsb(); /* ensure completion of the BP and TLB invalidation */
|
||||
isb(); /* synchronize context on this processor */
|
||||
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Invalidate the caches and then enable MMU for Cortex A53 processor.
|
||||
*
|
||||
* @param None.
|
||||
* @return None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_EnableMMU(void)
|
||||
{
|
||||
u32 Reg;
|
||||
Xil_DCacheInvalidate();
|
||||
Xil_ICacheInvalidate();
|
||||
|
||||
Reg = mfcp(SCTLR_EL1);
|
||||
|
||||
Reg |= 0x00000001U;
|
||||
/* Enable MMU */
|
||||
mtcp(SCTLR_EL1, Reg);
|
||||
|
||||
dsb(); /* ensure completion of the BP and TLB invalidation */
|
||||
isb(); /* synchronize context on this processor */
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Disable MMU for Cortex A53 processors. This function invalidates the TLBs
|
||||
* and flushed the D Caches before disabling the MMU and D cache.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_DisableMMU(void)
|
||||
{
|
||||
|
||||
u32 Reg;
|
||||
|
||||
mtcptlbi(ALLE3);
|
||||
Xil_DCacheFlush();
|
||||
|
||||
Reg = mfcp(SCTLR_EL1);
|
||||
Reg &= ~(0x00000001U);
|
||||
/*Disable mmu*/
|
||||
mtcp(SCTLR_EL1, Reg);
|
||||
dsb(); /* ensure completion of the BP and TLB invalidation */
|
||||
isb(); /* synchronize context on this processor */
|
||||
}
|
92
lib/bsp/standalone/src/cortexa53/xil_mmu.h
Normal file
92
lib/bsp/standalone/src/cortexa53/xil_mmu.h
Normal file
|
@ -0,0 +1,92 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xil_mmu.h
|
||||
*
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_MMU_H
|
||||
#define XIL_MMU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib);
|
||||
void Xil_EnableMMU(void);
|
||||
void Xil_DisableMMU(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XIL_MMU_H */
|
329
lib/bsp/standalone/src/cortexa53/xil_printf.c
Normal file
329
lib/bsp/standalone/src/cortexa53/xil_printf.c
Normal file
|
@ -0,0 +1,329 @@
|
|||
/*---------------------------------------------------*/
|
||||
/* Modified from : */
|
||||
/* Public Domain version of printf */
|
||||
/* Rud Merriam, Compsult, Inc. Houston, Tx. */
|
||||
/* For Embedded Systems Programming, 1991 */
|
||||
/* */
|
||||
/*---------------------------------------------------*/
|
||||
#include "xil_printf.h"
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include <ctype.h>
|
||||
#include <string.h>
|
||||
#include <stdarg.h>
|
||||
|
||||
typedef struct params_s {
|
||||
s32 len;
|
||||
s32 num1;
|
||||
s32 num2;
|
||||
char8 pad_character;
|
||||
s32 do_padding;
|
||||
s32 left_flag;
|
||||
} params_t;
|
||||
|
||||
static void padding( const s32 l_flag,const params_t *par);
|
||||
static void outs(const charptr lp, params_t *par);
|
||||
static void outnum( const s32 n, const s32 base, params_t *par);
|
||||
static s32 getnum( charptr* linep);
|
||||
|
||||
/*---------------------------------------------------*/
|
||||
/* The purpose of this routine is to output data the */
|
||||
/* same as the standard printf function without the */
|
||||
/* overhead most run-time libraries involve. Usually */
|
||||
/* the printf brings in many kilobytes of code and */
|
||||
/* that is unacceptable in most embedded systems. */
|
||||
/*---------------------------------------------------*/
|
||||
|
||||
|
||||
/*---------------------------------------------------*/
|
||||
/* */
|
||||
/* This routine puts pad characters into the output */
|
||||
/* buffer. */
|
||||
/* */
|
||||
static void padding( const s32 l_flag, const params_t *par)
|
||||
{
|
||||
s32 i;
|
||||
|
||||
if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
|
||||
i=(par->len);
|
||||
for (; i<(par->num1); i++) {
|
||||
outbyte( par->pad_character);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------*/
|
||||
/* */
|
||||
/* This routine moves a string to the output buffer */
|
||||
/* as directed by the padding and positioning flags. */
|
||||
/* */
|
||||
static void outs(const charptr lp, params_t *par)
|
||||
{
|
||||
charptr LocalPtr;
|
||||
LocalPtr = lp;
|
||||
/* pad on left if needed */
|
||||
if(LocalPtr != NULL) {
|
||||
par->len = (s32)strlen( LocalPtr);
|
||||
}
|
||||
padding( !(par->left_flag), par);
|
||||
|
||||
/* Move string to the buffer */
|
||||
while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
|
||||
(par->num2)--;
|
||||
outbyte(*LocalPtr);
|
||||
LocalPtr += 1;
|
||||
}
|
||||
|
||||
/* Pad on right if needed */
|
||||
/* CR 439175 - elided next stmt. Seemed bogus. */
|
||||
/* par->len = strlen( lp) */
|
||||
padding( par->left_flag, par);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------*/
|
||||
/* */
|
||||
/* This routine moves a number to the output buffer */
|
||||
/* as directed by the padding and positioning flags. */
|
||||
/* */
|
||||
|
||||
static void outnum( const s32 n, const s32 base, params_t *par)
|
||||
{
|
||||
charptr cp;
|
||||
s32 negative;
|
||||
s32 i;
|
||||
char8 outbuf[32];
|
||||
const char8 digits[] = "0123456789ABCDEF";
|
||||
s32 num;
|
||||
for(i = 0; i<32; i++) {
|
||||
outbuf[i] = '0';
|
||||
}
|
||||
|
||||
/* Check if number is negative */
|
||||
if ((base == 10) && (n < 0L)) {
|
||||
negative = 1;
|
||||
num =(-(n));
|
||||
}
|
||||
else{
|
||||
num = (n);
|
||||
negative = 0;
|
||||
}
|
||||
|
||||
/* Build number (backwards) in outbuf */
|
||||
i = 0;
|
||||
do {
|
||||
outbuf[i] = digits[(num % base)];
|
||||
i++;
|
||||
num /= base;
|
||||
} while (num > 0);
|
||||
|
||||
if (negative != 0) {
|
||||
outbuf[i] = '-';
|
||||
i++;
|
||||
}
|
||||
|
||||
outbuf[i] = 0;
|
||||
i--;
|
||||
|
||||
/* Move the converted number to the buffer and */
|
||||
/* add in the padding where needed. */
|
||||
par->len = (s32)strlen(outbuf);
|
||||
padding( !(par->left_flag), par);
|
||||
while (&outbuf[i] >= outbuf) {
|
||||
outbyte( outbuf[i] );
|
||||
i--;
|
||||
}
|
||||
padding( par->left_flag, par);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------*/
|
||||
/* */
|
||||
/* This routine gets a number from the format */
|
||||
/* string. */
|
||||
/* */
|
||||
static s32 getnum( charptr* linep)
|
||||
{
|
||||
s32 n;
|
||||
s32 ResultIsDigit = 0;
|
||||
charptr cptr;
|
||||
n = 0;
|
||||
cptr = *linep;
|
||||
if(cptr != NULL){
|
||||
ResultIsDigit = isdigit(((s32)*cptr));
|
||||
}
|
||||
while (ResultIsDigit != 0) {
|
||||
if(cptr != NULL){
|
||||
n = ((n*10) + (((s32)*cptr) - (s32)'0'));
|
||||
cptr += 1;
|
||||
if(cptr != NULL){
|
||||
ResultIsDigit = isdigit(((s32)*cptr));
|
||||
}
|
||||
}
|
||||
ResultIsDigit = isdigit(((s32)*cptr));
|
||||
}
|
||||
*linep = ((charptr )(cptr));
|
||||
return(n);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------*/
|
||||
/* */
|
||||
/* This routine operates just like a printf/sprintf */
|
||||
/* routine. It outputs a set of data under the */
|
||||
/* control of a formatting string. Not all of the */
|
||||
/* standard C format control are supported. The ones */
|
||||
/* provided are primarily those needed for embedded */
|
||||
/* systems work. Primarily the floating point */
|
||||
/* routines are omitted. Other formats could be */
|
||||
/* added easily by following the examples shown for */
|
||||
/* the supported formats. */
|
||||
/* */
|
||||
|
||||
/* void esp_printf( const func_ptr f_ptr,
|
||||
const charptr ctrl1, ...) */
|
||||
void xil_printf( char8 *ctrl1, ...)
|
||||
{
|
||||
s32 Check;
|
||||
s32 long_flag;
|
||||
s32 dot_flag;
|
||||
|
||||
params_t par;
|
||||
|
||||
char8 ch;
|
||||
va_list argp;
|
||||
char8 *ctrl = (char8 *)ctrl1;
|
||||
|
||||
va_start( argp, ctrl1);
|
||||
|
||||
while ((ctrl != NULL) && (*ctrl != (char8)0)) {
|
||||
|
||||
/* move format string chars to buffer until a */
|
||||
/* format control is found. */
|
||||
if (*ctrl != '%') {
|
||||
outbyte(*ctrl);
|
||||
ctrl += 1;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* initialize all the flags for this format. */
|
||||
dot_flag = 0;
|
||||
long_flag = 0;
|
||||
par.left_flag = 0;
|
||||
par.do_padding = 0;
|
||||
par.pad_character = ' ';
|
||||
par.num2=32767;
|
||||
par.num1=0;
|
||||
par.len=0;
|
||||
|
||||
try_next:
|
||||
if(ctrl != NULL) {
|
||||
ctrl += 1;
|
||||
}
|
||||
if(ctrl != NULL) {
|
||||
ch = *ctrl;
|
||||
}
|
||||
else {
|
||||
ch = *ctrl;
|
||||
}
|
||||
|
||||
if (isdigit((s32)ch) != 0) {
|
||||
if (dot_flag != 0) {
|
||||
par.num2 = getnum(&ctrl);
|
||||
}
|
||||
else {
|
||||
if (ch == '0') {
|
||||
par.pad_character = '0';
|
||||
}
|
||||
if(ctrl != NULL) {
|
||||
par.num1 = getnum(&ctrl);
|
||||
}
|
||||
par.do_padding = 1;
|
||||
}
|
||||
if(ctrl != NULL) {
|
||||
ctrl -= 1;
|
||||
}
|
||||
goto try_next;
|
||||
}
|
||||
|
||||
switch (tolower((s32)ch)) {
|
||||
case '%':
|
||||
outbyte( '%');
|
||||
Check = 1;
|
||||
break;
|
||||
|
||||
case '-':
|
||||
par.left_flag = 1;
|
||||
Check = 0;
|
||||
break;
|
||||
|
||||
case '.':
|
||||
dot_flag = 1;
|
||||
Check = 0;
|
||||
break;
|
||||
|
||||
case 'l':
|
||||
long_flag = 1;
|
||||
Check = 0;
|
||||
break;
|
||||
|
||||
case 'd':
|
||||
if ((long_flag != 0) || (ch == 'D')) {
|
||||
outnum( va_arg(argp, s32), 10L, &par);
|
||||
}
|
||||
else {
|
||||
outnum( va_arg(argp, s32), 10L, &par);
|
||||
}
|
||||
Check = 1;
|
||||
break;
|
||||
case 'x':
|
||||
outnum((s32)va_arg(argp, s32), 16L, &par);
|
||||
Check = 1;
|
||||
break;
|
||||
|
||||
case 's':
|
||||
outs( va_arg( argp, char *), &par);
|
||||
Check = 1;
|
||||
break;
|
||||
|
||||
case 'c':
|
||||
outbyte( va_arg( argp, s32));
|
||||
Check = 1;
|
||||
break;
|
||||
|
||||
case '\\':
|
||||
switch (*ctrl) {
|
||||
case 'a':
|
||||
outbyte( ((char8)0x07));
|
||||
break;
|
||||
case 'h':
|
||||
outbyte( ((char8)0x08));
|
||||
break;
|
||||
case 'r':
|
||||
outbyte( ((char8)0x0D));
|
||||
break;
|
||||
case 'n':
|
||||
outbyte( ((char8)0x0D));
|
||||
outbyte( ((char8)0x0A));
|
||||
break;
|
||||
default:
|
||||
outbyte( *ctrl);
|
||||
break;
|
||||
}
|
||||
ctrl += 1;
|
||||
Check = 0;
|
||||
break;
|
||||
|
||||
default:
|
||||
Check = 1;
|
||||
break;
|
||||
}
|
||||
if(Check == 1) {
|
||||
if(ctrl != NULL) {
|
||||
ctrl += 1;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
goto try_next;
|
||||
}
|
||||
va_end( argp);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------*/
|
44
lib/bsp/standalone/src/cortexa53/xil_printf.h
Normal file
44
lib/bsp/standalone/src/cortexa53/xil_printf.h
Normal file
|
@ -0,0 +1,44 @@
|
|||
#ifndef XIL_PRINTF_H
|
||||
#define XIL_PRINTF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ctype.h>
|
||||
#include <string.h>
|
||||
#include <stdarg.h>
|
||||
#include "xil_types.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/*----------------------------------------------------*/
|
||||
/* Use the following parameter passing structure to */
|
||||
/* make xil_printf re-entrant. */
|
||||
/*----------------------------------------------------*/
|
||||
|
||||
struct params_s;
|
||||
|
||||
|
||||
/*---------------------------------------------------*/
|
||||
/* The purpose of this routine is to output data the */
|
||||
/* same as the standard printf function without the */
|
||||
/* overhead most run-time libraries involve. Usually */
|
||||
/* the printf brings in many kilobytes of code and */
|
||||
/* that is unacceptable in most embedded systems. */
|
||||
/*---------------------------------------------------*/
|
||||
|
||||
typedef char8* charptr;
|
||||
typedef s32 (*func_ptr)(int c);
|
||||
|
||||
/* */
|
||||
|
||||
void xil_printf( char8 *ctrl1, ...);
|
||||
void print( const char8 *ptr);
|
||||
extern void outbyte (char8 c);
|
||||
extern char8 inbyte(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
368
lib/bsp/standalone/src/cortexa53/xparameters_ps.h
Normal file
368
lib/bsp/standalone/src/cortexa53/xparameters_ps.h
Normal file
|
@ -0,0 +1,368 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xparameters_ps.h
|
||||
*
|
||||
* This file contains the address definitions for the hard peripherals
|
||||
* attached to the ARM Cortex A53 core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _XPARAMETERS_PS_H_
|
||||
#define _XPARAMETERS_PS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/*
|
||||
* This block contains constant declarations for the peripherals
|
||||
* within the hardblock
|
||||
*/
|
||||
|
||||
/* Canonical definitions for DDR MEMORY */
|
||||
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
|
||||
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
|
||||
|
||||
/* Canonical definitions for Interrupts */
|
||||
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
|
||||
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
|
||||
#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
|
||||
#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
|
||||
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
|
||||
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
|
||||
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
|
||||
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
|
||||
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
|
||||
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
|
||||
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
|
||||
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
|
||||
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
|
||||
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
|
||||
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
|
||||
#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
|
||||
#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
|
||||
#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
|
||||
#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
|
||||
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
|
||||
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
|
||||
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
|
||||
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
|
||||
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
|
||||
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
|
||||
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
|
||||
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
|
||||
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
|
||||
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
|
||||
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
|
||||
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
|
||||
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
|
||||
#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
|
||||
#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
|
||||
#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
|
||||
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
|
||||
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
|
||||
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
|
||||
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
|
||||
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
|
||||
|
||||
|
||||
#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
|
||||
#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
|
||||
|
||||
|
||||
|
||||
/* Canonical definitions for DMAC */
|
||||
|
||||
|
||||
/* Canonical definitions for WDT */
|
||||
|
||||
/* Canonical definitions for SLCR */
|
||||
#define XPAR_XSLCR_NUM_INSTANCES 1U
|
||||
#define XPAR_XSLCR_0_DEVICE_ID 0U
|
||||
#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
|
||||
|
||||
/* Canonical definitions for SCU GIC */
|
||||
#define XPAR_SCUGIC_NUM_INSTANCES 1U
|
||||
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
|
||||
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
|
||||
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
|
||||
#define XPAR_SCUGIC_ACK_BEFORE 0U
|
||||
|
||||
/* Canonical definitions for Global Timer */
|
||||
#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
|
||||
#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
|
||||
#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
|
||||
#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
|
||||
|
||||
|
||||
/* Xilinx Parallel Flash Library (XilFlash) User Settings */
|
||||
#define XPAR_AXI_EMC
|
||||
|
||||
|
||||
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
|
||||
|
||||
|
||||
/*
|
||||
* This block contains constant declarations for the peripherals
|
||||
* within the hardblock. These have been put for backwards compatibilty
|
||||
*/
|
||||
|
||||
#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
|
||||
#define XPS_UART0_BASEADDR 0xFF000000U
|
||||
#define XPS_UART1_BASEADDR 0xFF010000U
|
||||
#define XPS_I2C0_BASEADDR 0xFF020000U
|
||||
#define XPS_I2C1_BASEADDR 0xFF030000U
|
||||
#define XPS_SPI0_BASEADDR 0xFF040000U
|
||||
#define XPS_SPI1_BASEADDR 0xFF050000U
|
||||
#define XPS_CAN0_BASEADDR 0xFF060000U
|
||||
#define XPS_CAN1_BASEADDR 0xFF070000U
|
||||
#define XPS_GPIO_BASEADDR 0xFF0A0000U
|
||||
#define XPS_GEM0_BASEADDR 0xFF0B0000U
|
||||
#define XPS_GEM1_BASEADDR 0xFF0C0000U
|
||||
#define XPS_GEM2_BASEADDR 0xFF0D0000U
|
||||
#define XPS_GEM3_BASEADDR 0xFF0E0000U
|
||||
#define XPS_QSPI_BASEADDR 0xFF0F0000U
|
||||
#define XPS_NAND_BASEADDR 0xFF100000U
|
||||
#define XPS_TTC0_BASEADDR 0xFF110000U
|
||||
#define XPS_TTC1_BASEADDR 0xFF120000U
|
||||
#define XPS_TTC2_BASEADDR 0xFF130000U
|
||||
#define XPS_TTC3_BASEADDR 0xFF140000U
|
||||
#define XPS_WDT_BASEADDR 0xFF150000U
|
||||
#define XPS_SDIO0_BASEADDR 0xFF160000U
|
||||
#define XPS_SDIO1_BASEADDR 0xFF170000U
|
||||
#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
|
||||
/*#define XPAR_XNANDPS8_0_BASEADDR 0xFF100000U */
|
||||
|
||||
|
||||
#define XPS_PARPORT_CRTL_BASEADDR 0x0000000U
|
||||
#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
|
||||
#define XPS_PARPORT0_BASEADDR 0xE2000000U
|
||||
#define XPS_PARPORT1_BASEADDR 0xE4000000U
|
||||
#define XPS_QSPI_LINEAR_BASEADDR 0xF0000000U
|
||||
#define XPS_DMAC0_NON_SEC_BASEADDR 0xFE507000U
|
||||
#define XPS_DMAC0_SEC_BASEADDR 0xFE5F0000U
|
||||
#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
|
||||
#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
|
||||
#define XPS_AFI0_BASEADDR 0xF8008000U
|
||||
#define XPS_AFI1_BASEADDR 0xF8009000U
|
||||
#define XPS_AFI2_BASEADDR 0xF800A000U
|
||||
#define XPS_AFI3_BASEADDR 0xF800B000U
|
||||
#define XPS_OCM_BASEADDR 0xF800C000U
|
||||
#define XPS_EFUSE_BASEADDR 0xF800D000U
|
||||
#define XPS_CORESIGHT_BASEADDR 0xF8800000U
|
||||
#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
|
||||
#define XPS_SCU_PERIPH_BASE 0xF9000000U
|
||||
#define XPS_L2CC_BASEADDR 0xFD3FD000U
|
||||
#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
|
||||
#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
|
||||
#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
|
||||
#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
|
||||
#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
|
||||
#define XPS_USB0_BASEADDR 0xE0002000U
|
||||
#define XPS_USB1_BASEADDR 0xE0003000U
|
||||
|
||||
|
||||
/* Shared Peripheral Interrupts (SPI) */
|
||||
|
||||
#define XPS_USB1_INT_ID 76U
|
||||
#define XPS_USB0_INT_ID 53U
|
||||
|
||||
#define XPS_NAND_INT_ID (32U + 32U)
|
||||
|
||||
#define XPS_FPGA1_INT_ID 62U
|
||||
#define XPS_FPGA2_INT_ID 63U
|
||||
#define XPS_FPGA3_INT_ID 64U
|
||||
#define XPS_FPGA4_INT_ID 65U
|
||||
#define XPS_FPGA5_INT_ID 66U
|
||||
#define XPS_FPGA6_INT_ID 67U
|
||||
#define XPS_FPGA7_INT_ID 68U
|
||||
#define XPS_DMA4_INT_ID 72U
|
||||
#define XPS_DMA5_INT_ID 73U
|
||||
#define XPS_DMA6_INT_ID 74U
|
||||
#define XPS_DMA7_INT_ID 75U
|
||||
#define XPS_FPGA8_INT_ID 84U
|
||||
#define XPS_FPGA9_INT_ID 85U
|
||||
#define XPS_FPGA10_INT_ID 86U
|
||||
#define XPS_FPGA11_INT_ID 87U
|
||||
#define XPS_FPGA12_INT_ID 88U
|
||||
#define XPS_FPGA13_INT_ID 89U
|
||||
#define XPS_FPGA14_INT_ID 90U
|
||||
#define XPS_FPGA15_INT_ID 91U
|
||||
|
||||
|
||||
#define XPS_OCMINTR_INT_ID (28U + 32U)
|
||||
#define XPS_QSPI_INT_ID (33U + 32U)
|
||||
#define XPS_GPIO_INT_ID (34U + 32U)
|
||||
#define XPS_WDT_INT_ID (106U + 32U)
|
||||
#define XPS_LP_WDT_INT_ID (69U + 32U)
|
||||
#define XPS_TTC0_0_INT_ID (53U + 32U)
|
||||
#define XPS_TTC0_1_INT_ID (54U + 32U)
|
||||
#define XPS_TTC0_2_INT_ID (55U + 32U)
|
||||
#define XPS_SDIO0_INT_ID (65U + 32U)
|
||||
#define XPS_I2C0_INT_ID (35U + 32U)
|
||||
#define XPS_SPI0_INT_ID (37U + 32U)
|
||||
#define XPS_UART0_INT_ID (39U + 32U)
|
||||
#define XPS_CAN0_INT_ID (41U + 32U)
|
||||
|
||||
/* FIXME */
|
||||
/*#define XPS_FPGA0_INT_ID 100U */
|
||||
|
||||
#define XPS_TTC1_0_INT_ID (56U + 32U)
|
||||
#define XPS_TTC1_1_INT_ID (57U + 32U)
|
||||
#define XPS_TTC1_2_INT_ID (58U + 32U)
|
||||
#define XPS_TTC2_0_INT_ID (59U + 32U)
|
||||
#define XPS_TTC2_1_INT_ID (60U + 32U)
|
||||
#define XPS_TTC2_2_INT_ID (61U + 32U)
|
||||
#define XPS_TTC3_0_INT_ID (62U + 32U)
|
||||
#define XPS_TTC3_1_INT_ID (63U + 32U)
|
||||
#define XPS_TTC3_2_INT_ID (64U + 32U)
|
||||
#define XPS_SDIO1_INT_ID (66U + 32U)
|
||||
#define XPS_I2C1_INT_ID (36U + 32U)
|
||||
#define XPS_SPI1_INT_ID (38U + 32U)
|
||||
#define XPS_UART1_INT_ID (40U + 32U)
|
||||
#define XPS_CAN1_INT_ID (42U + 32U)
|
||||
#define XPS_GEM0_INT_ID (73U + 32U)
|
||||
#define XPS_GEM0_WAKE_INT_ID (74U + 32U)
|
||||
#define XPS_GEM1_INT_ID (75U + 32U)
|
||||
#define XPS_GEM1_WAKE_INT_ID (76U + 32U)
|
||||
#define XPS_GEM2_INT_ID (77U + 32U)
|
||||
#define XPS_GEM2_WAKE_INT_ID (78U + 32U)
|
||||
#define XPS_GEM3_INT_ID (79U + 32U)
|
||||
#define XPS_GEM3_WAKE_INT_ID (80U + 32U)
|
||||
|
||||
/* Private Peripheral Interrupts (PPI) */
|
||||
/*#define XPS_GLOBAL_TMR_INT_ID 27U SCU Global Timer interrupt */
|
||||
/*#define XPS_FIQ_INT_ID 28U FIQ from FPGA fabric */
|
||||
/*#define XPS_SCU_TMR_INT_ID 29U SCU Private Timer interrupt */
|
||||
/*#define XPS_SCU_WDT_INT_ID 30U SCU Private WDT interrupt */
|
||||
/*#define XPS_IRQ_INT_ID 31U IRQ from FPGA fabric */
|
||||
|
||||
|
||||
/* REDEFINES for TEST APP */
|
||||
/* Definitions for UART */
|
||||
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
|
||||
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
|
||||
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
|
||||
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
|
||||
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
|
||||
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
|
||||
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
|
||||
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
|
||||
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
|
||||
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
|
||||
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
|
||||
|
||||
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
|
||||
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
|
||||
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
|
||||
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
|
||||
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
|
||||
|
||||
#define XPAR_XADCPS_NUM_INSTANCES 1U
|
||||
#define XPAR_XADCPS_0_DEVICE_ID 0U
|
||||
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
|
||||
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
|
||||
|
||||
/* For backwards compatibilty */
|
||||
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
|
||||
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
|
||||
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
|
||||
|
||||
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
|
||||
|
||||
#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
|
||||
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
|
||||
#endif
|
||||
|
||||
#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
|
||||
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
|
||||
#endif
|
||||
|
||||
#define XPAR_SCUTIMER_DEVICE_ID 0U
|
||||
#define XPAR_SCUWDT_DEVICE_ID 0U
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* protection macro */
|
68
lib/bsp/standalone/src/cortexa53/xpseudo_asm.h
Normal file
68
lib/bsp/standalone/src/cortexa53/xpseudo_asm.h
Normal file
|
@ -0,0 +1,68 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xpseudo_asm.h
|
||||
*
|
||||
* This header file contains macros for using inline assembler code.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XPSEUDO_ASM_H
|
||||
#define XPSEUDO_ASM_H
|
||||
#include "xreg_cortexa53.h"
|
||||
#ifdef __GNUC__
|
||||
#include "xpseudo_asm_gcc.h"
|
||||
#else
|
||||
#include "xpseudo_asm_rvct.h"
|
||||
#endif
|
||||
|
||||
#endif /* XPSEUDO_ASM_H */
|
226
lib/bsp/standalone/src/cortexa53/xreg_cortexa53.h
Normal file
226
lib/bsp/standalone/src/cortexa53/xreg_cortexa53.h
Normal file
|
@ -0,0 +1,226 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xreg_cortexa53.h
|
||||
*
|
||||
* This header file contains definitions for using inline assembler code. It is
|
||||
* written specifically for the GNU compiler.
|
||||
*
|
||||
* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along
|
||||
* with the positions of the bits within the registers.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XREG_CORTEXA53_H
|
||||
#define XREG_CORTEXA53_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
/* GPRs */
|
||||
#define XREG_GPR0 r0
|
||||
#define XREG_GPR1 r1
|
||||
#define XREG_GPR2 r2
|
||||
#define XREG_GPR3 r3
|
||||
#define XREG_GPR4 r4
|
||||
#define XREG_GPR5 r5
|
||||
#define XREG_GPR6 r6
|
||||
#define XREG_GPR7 r7
|
||||
#define XREG_GPR8 r8
|
||||
#define XREG_GPR9 r9
|
||||
#define XREG_GPR10 r10
|
||||
#define XREG_GPR11 r11
|
||||
#define XREG_GPR12 r12
|
||||
#define XREG_GPR13 r13
|
||||
#define XREG_GPR14 r14
|
||||
#define XREG_GPR15 r15
|
||||
#define XREG_CPSR cpsr
|
||||
|
||||
/* Coprocessor number defines */
|
||||
#define XREG_CP0 0
|
||||
#define XREG_CP1 1
|
||||
#define XREG_CP2 2
|
||||
#define XREG_CP3 3
|
||||
#define XREG_CP4 4
|
||||
#define XREG_CP5 5
|
||||
#define XREG_CP6 6
|
||||
#define XREG_CP7 7
|
||||
#define XREG_CP8 8
|
||||
#define XREG_CP9 9
|
||||
#define XREG_CP10 10
|
||||
#define XREG_CP11 11
|
||||
#define XREG_CP12 12
|
||||
#define XREG_CP13 13
|
||||
#define XREG_CP14 14
|
||||
#define XREG_CP15 15
|
||||
|
||||
/* Coprocessor control register defines */
|
||||
#define XREG_CR0 cr0
|
||||
#define XREG_CR1 cr1
|
||||
#define XREG_CR2 cr2
|
||||
#define XREG_CR3 cr3
|
||||
#define XREG_CR4 cr4
|
||||
#define XREG_CR5 cr5
|
||||
#define XREG_CR6 cr6
|
||||
#define XREG_CR7 cr7
|
||||
#define XREG_CR8 cr8
|
||||
#define XREG_CR9 cr9
|
||||
#define XREG_CR10 cr10
|
||||
#define XREG_CR11 cr11
|
||||
#define XREG_CR12 cr12
|
||||
#define XREG_CR13 cr13
|
||||
#define XREG_CR14 cr14
|
||||
#define XREG_CR15 cr15
|
||||
|
||||
/* Current Processor Status Register (CPSR) Bits */
|
||||
#define XREG_CPSR_THUMB_MODE 0x20
|
||||
#define XREG_CPSR_MODE_BITS 0x1F
|
||||
#define XREG_CPSR_SYSTEM_MODE 0x1F
|
||||
#define XREG_CPSR_UNDEFINED_MODE 0x1B
|
||||
#define XREG_CPSR_DATA_ABORT_MODE 0x17
|
||||
#define XREG_CPSR_SVC_MODE 0x13
|
||||
#define XREG_CPSR_IRQ_MODE 0x12
|
||||
#define XREG_CPSR_FIQ_MODE 0x11
|
||||
#define XREG_CPSR_USER_MODE 0x10
|
||||
|
||||
#define XREG_CPSR_IRQ_ENABLE 0x80
|
||||
#define XREG_CPSR_FIQ_ENABLE 0x40
|
||||
|
||||
#define XREG_CPSR_N_BIT 0x80000000U
|
||||
#define XREG_CPSR_Z_BIT 0x40000000U
|
||||
#define XREG_CPSR_C_BIT 0x20000000U
|
||||
#define XREG_CPSR_V_BIT 0x10000000U
|
||||
|
||||
|
||||
|
||||
/* MPE register definitions */
|
||||
#define XREG_FPSID c0
|
||||
#define XREG_FPSCR c1
|
||||
#define XREG_MVFR1 c6
|
||||
#define XREG_MVFR0 c7
|
||||
#define XREG_FPEXC c8
|
||||
#define XREG_FPINST c9
|
||||
#define XREG_FPINST2 c10
|
||||
|
||||
/* FPSID bits */
|
||||
#define XREG_FPSID_IMPLEMENTER_BIT (24U)
|
||||
#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT)
|
||||
#define XREG_FPSID_SOFTWARE (0X00000001U<<23U)
|
||||
#define XREG_FPSID_ARCH_BIT (16U)
|
||||
#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT)
|
||||
#define XREG_FPSID_PART_BIT (8U)
|
||||
#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT)
|
||||
#define XREG_FPSID_VARIANT_BIT (4U)
|
||||
#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT)
|
||||
#define XREG_FPSID_REV_BIT (0U)
|
||||
#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT)
|
||||
|
||||
/* FPSCR bits */
|
||||
#define XREG_FPSCR_N_BIT (0X00000001U << 31U)
|
||||
#define XREG_FPSCR_Z_BIT (0X00000001U << 30U)
|
||||
#define XREG_FPSCR_C_BIT (0X00000001U << 29U)
|
||||
#define XREG_FPSCR_V_BIT (0X00000001U << 28U)
|
||||
#define XREG_FPSCR_QC (0X00000001U << 27U)
|
||||
#define XREG_FPSCR_AHP (0X00000001U << 26U)
|
||||
#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U)
|
||||
#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U)
|
||||
#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U)
|
||||
#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U)
|
||||
#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U)
|
||||
#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U)
|
||||
#define XREG_FPSCR_RMODE_BIT (22U)
|
||||
#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT)
|
||||
#define XREG_FPSCR_STRIDE_BIT (20U)
|
||||
#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT)
|
||||
#define XREG_FPSCR_LENGTH_BIT (16U)
|
||||
#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT)
|
||||
#define XREG_FPSCR_IDC (0X00000001U << 7U)
|
||||
#define XREG_FPSCR_IXC (0X00000001U << 4U)
|
||||
#define XREG_FPSCR_UFC (0X00000001U << 3U)
|
||||
#define XREG_FPSCR_OFC (0X00000001U << 2U)
|
||||
#define XREG_FPSCR_DZC (0X00000001U << 1U)
|
||||
#define XREG_FPSCR_IOC (0X00000001U << 0U)
|
||||
|
||||
/* MVFR0 bits */
|
||||
#define XREG_MVFR0_RMODE_BIT (28U)
|
||||
#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT)
|
||||
#define XREG_MVFR0_SHORT_VEC_BIT (24U)
|
||||
#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
|
||||
#define XREG_MVFR0_SQRT_BIT (20U)
|
||||
#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT)
|
||||
#define XREG_MVFR0_DIVIDE_BIT (16U)
|
||||
#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
|
||||
#define XREG_MVFR0_EXEC_TRAP_BIT (0X00000012U)
|
||||
#define XREG_MVFR0_EXEC_TRAP_MASK (0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
|
||||
#define XREG_MVFR0_DP_BIT (8U)
|
||||
#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT)
|
||||
#define XREG_MVFR0_SP_BIT (4U)
|
||||
#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT)
|
||||
#define XREG_MVFR0_A_SIMD_BIT (0U)
|
||||
#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT)
|
||||
|
||||
/* FPEXC bits */
|
||||
#define XREG_FPEXC_EX (0X00000001U << 31U)
|
||||
#define XREG_FPEXC_EN (0X00000001U << 30U)
|
||||
#define XREG_FPEXC_DEX (0X00000001U << 29U)
|
||||
|
||||
|
||||
#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U)
|
||||
#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XREG_CORTEXA53_H */
|
441
lib/bsp/standalone/src/cortexa53/xstatus.h
Normal file
441
lib/bsp/standalone/src/cortexa53/xstatus.h
Normal file
|
@ -0,0 +1,441 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xstatus.h
|
||||
*
|
||||
* This file contains Xilinx software status codes. Status codes have their
|
||||
* own data type called int. These codes are used throughout the Xilinx
|
||||
* device drivers.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XSTATUS_H /* prevent circular inclusions */
|
||||
#define XSTATUS_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/*********************** Common statuses 0 - 500 *****************************/
|
||||
|
||||
#define XST_SUCCESS 0L
|
||||
#define XST_FAILURE 1L
|
||||
#define XST_DEVICE_NOT_FOUND 2L
|
||||
#define XST_DEVICE_BLOCK_NOT_FOUND 3L
|
||||
#define XST_INVALID_VERSION 4L
|
||||
#define XST_DEVICE_IS_STARTED 5L
|
||||
#define XST_DEVICE_IS_STOPPED 6L
|
||||
#define XST_FIFO_ERROR 7L /* an error occurred during an
|
||||
operation with a FIFO such as
|
||||
an underrun or overrun, this
|
||||
error requires the device to
|
||||
be reset */
|
||||
#define XST_RESET_ERROR 8L /* an error occurred which requires
|
||||
the device to be reset */
|
||||
#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
|
||||
typically requires the device
|
||||
using the DMA to be reset */
|
||||
#define XST_NOT_POLLED 10L /* the device is not configured for
|
||||
polled mode operation */
|
||||
#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
|
||||
the specified data into */
|
||||
#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
|
||||
to hold the expected data */
|
||||
#define XST_NO_DATA 13L /* there was no data available */
|
||||
#define XST_REGISTER_ERROR 14L /* a register did not contain the
|
||||
expected value */
|
||||
#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
|
||||
into the function */
|
||||
#define XST_NOT_SGDMA 16L /* the device is not configured for
|
||||
scatter-gather DMA operation */
|
||||
#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
|
||||
#define XST_NO_CALLBACK 18L /* a callback has not yet been
|
||||
registered */
|
||||
#define XST_NO_FEATURE 19L /* device is not configured with
|
||||
the requested feature */
|
||||
#define XST_NOT_INTERRUPT 20L /* device is not configured for
|
||||
interrupt mode operation */
|
||||
#define XST_DEVICE_BUSY 21L /* device is busy */
|
||||
#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
|
||||
have maxed out */
|
||||
#define XST_IS_STARTED 23L /* used when part of device is
|
||||
already started i.e.
|
||||
sub channel */
|
||||
#define XST_IS_STOPPED 24L /* used when part of device is
|
||||
already stopped i.e.
|
||||
sub channel */
|
||||
#define XST_DATA_LOST 26L /* driver defined error */
|
||||
#define XST_RECV_ERROR 27L /* generic receive error */
|
||||
#define XST_SEND_ERROR 28L /* generic transmit error */
|
||||
#define XST_NOT_ENABLED 29L /* a requested service is not
|
||||
available because it has not
|
||||
been enabled */
|
||||
|
||||
/***************** Utility Component statuses 401 - 500 *********************/
|
||||
|
||||
#define XST_MEMTEST_FAILED 401L /* memory test failed */
|
||||
|
||||
|
||||
/***************** Common Components statuses 501 - 1000 *********************/
|
||||
|
||||
/********************* Packet Fifo statuses 501 - 510 ************************/
|
||||
|
||||
#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
|
||||
#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
|
||||
#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
|
||||
was invalid after reset */
|
||||
#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
|
||||
#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
|
||||
* empty and full simultaneously
|
||||
*/
|
||||
|
||||
/************************** DMA statuses 511 - 530 ***************************/
|
||||
|
||||
#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
|
||||
failed */
|
||||
#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
|
||||
was invalid after reset */
|
||||
#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
|
||||
no buffer descriptors ready
|
||||
to be processed */
|
||||
#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
|
||||
#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
|
||||
#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
|
||||
the scatter gather list are
|
||||
being used */
|
||||
#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
|
||||
descriptor which is to be
|
||||
copied over in the scatter
|
||||
list is locked */
|
||||
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
|
||||
put into the scatter gather
|
||||
list to be commited */
|
||||
#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
|
||||
specified was larger than the
|
||||
total # of buffer descriptors
|
||||
in the scatter gather list */
|
||||
#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
|
||||
already been created */
|
||||
#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
|
||||
been created */
|
||||
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
|
||||
being started was not committed
|
||||
to the list */
|
||||
#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
|
||||
has already been used by the
|
||||
hardware so it can't be reused
|
||||
*/
|
||||
#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
|
||||
error */
|
||||
#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
|
||||
error */
|
||||
|
||||
/************************** IPIF statuses 531 - 550 ***************************/
|
||||
|
||||
#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
|
||||
was passed into the function */
|
||||
#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
|
||||
reset was not valid */
|
||||
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
|
||||
status register did not read
|
||||
back correctly */
|
||||
#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
|
||||
register did not reset when
|
||||
acked */
|
||||
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
|
||||
register was not updated when
|
||||
other registers changed */
|
||||
#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
|
||||
status register did not read
|
||||
back correctly */
|
||||
#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
|
||||
did not reset when acked */
|
||||
#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
|
||||
not updated correctly when other
|
||||
registers changed */
|
||||
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
|
||||
register did not indicate the
|
||||
expected value */
|
||||
#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
|
||||
did not indicate the expected
|
||||
value */
|
||||
#define XST_IPIF_ERROR 541L /* generic ipif error */
|
||||
|
||||
/****************** Device specific statuses 1001 - 4095 *********************/
|
||||
|
||||
/********************* Ethernet statuses 1001 - 1050 *************************/
|
||||
|
||||
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
|
||||
* to hold the minimum number of
|
||||
* buffers or descriptors */
|
||||
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
|
||||
#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
|
||||
#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
|
||||
#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
|
||||
#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
|
||||
#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
|
||||
* collision on polled send */
|
||||
|
||||
/*********************** UART statuses 1051 - 1075 ***************************/
|
||||
#define XST_UART
|
||||
|
||||
#define XST_UART_INIT_ERROR 1051L
|
||||
#define XST_UART_START_ERROR 1052L
|
||||
#define XST_UART_CONFIG_ERROR 1053L
|
||||
#define XST_UART_TEST_FAIL 1054L
|
||||
#define XST_UART_BAUD_ERROR 1055L
|
||||
#define XST_UART_BAUD_RANGE 1056L
|
||||
|
||||
|
||||
/************************ IIC statuses 1076 - 1100 ***************************/
|
||||
|
||||
#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
|
||||
#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
|
||||
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
|
||||
/* general call address */
|
||||
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
|
||||
/* value after reset not valid */
|
||||
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
|
||||
/* value after reset not valid */
|
||||
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
|
||||
/* value after reset not valid */
|
||||
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
|
||||
/* value after reset not valid */
|
||||
#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
|
||||
/* didn't return value written */
|
||||
#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
|
||||
/* didn't return value written */
|
||||
#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
|
||||
/* didn't return value written */
|
||||
#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
|
||||
/* didn't return value written */
|
||||
#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
|
||||
/* didn't return written value */
|
||||
#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
|
||||
|
||||
/*********************** ATMC statuses 1101 - 1125 ***************************/
|
||||
|
||||
#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
|
||||
controller hit the max value
|
||||
which requires the statistics
|
||||
to be cleared */
|
||||
|
||||
/*********************** Flash statuses 1126 - 1150 **************************/
|
||||
|
||||
#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
|
||||
*/
|
||||
#define XST_FLASH_READY 1127L /* Flash is ready for commands */
|
||||
#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
|
||||
error. Use XFlash_DeviceControl
|
||||
to retrieve device specific codes
|
||||
*/
|
||||
#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
|
||||
*/
|
||||
#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
|
||||
*/
|
||||
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
|
||||
driver */
|
||||
#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
|
||||
#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
|
||||
#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
|
||||
aborted due to a timeout */
|
||||
#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
|
||||
addressible range */
|
||||
#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
|
||||
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
|
||||
write/erase function with
|
||||
XFL_NON_BLOCKING_WRITE/ERASE
|
||||
option cleared */
|
||||
#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
|
||||
|
||||
/*********************** SPI statuses 1151 - 1175 ****************************/
|
||||
|
||||
#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
|
||||
#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
|
||||
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
|
||||
#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
|
||||
#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
|
||||
#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
|
||||
* selected */
|
||||
#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
|
||||
#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
|
||||
*/
|
||||
#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
|
||||
#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
|
||||
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
|
||||
|
||||
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
|
||||
|
||||
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
|
||||
|
||||
#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
|
||||
* one master assigned to two or more
|
||||
* priorities, or one master not
|
||||
* assigned to any priority
|
||||
*/
|
||||
#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
|
||||
* priority levels without first
|
||||
* suspending the use of priority
|
||||
* levels
|
||||
*/
|
||||
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
|
||||
* bus parking was not enabled
|
||||
*/
|
||||
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
|
||||
* priority mode to allow the
|
||||
* priorities to be changed
|
||||
*/
|
||||
|
||||
/************************ Intc statuses 1201 - 1225 **************************/
|
||||
|
||||
#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
|
||||
#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
|
||||
|
||||
/********************** TmrCtr statuses 1226 - 1250 **************************/
|
||||
|
||||
#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
|
||||
|
||||
/********************** WdtTb statuses 1251 - 1275 ***************************/
|
||||
|
||||
#define XST_WDTTB_TIMER_FAILED 1251L
|
||||
|
||||
/********************** PlbArb statuses 1276 - 1300 **************************/
|
||||
|
||||
#define XST_PLBARB_FAIL_SELFTEST 1276L
|
||||
|
||||
/********************** Plb2Opb statuses 1301 - 1325 *************************/
|
||||
|
||||
#define XST_PLB2OPB_FAIL_SELFTEST 1301L
|
||||
|
||||
/********************** Opb2Plb statuses 1326 - 1350 *************************/
|
||||
|
||||
#define XST_OPB2PLB_FAIL_SELFTEST 1326L
|
||||
|
||||
/********************** SysAce statuses 1351 - 1360 **************************/
|
||||
|
||||
#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
|
||||
|
||||
/********************** PCI Bridge statuses 1361 - 1375 **********************/
|
||||
|
||||
#define XST_PCI_INVALID_ADDRESS 1361L
|
||||
|
||||
/********************** FlexRay constants 1400 - 1409 *************************/
|
||||
|
||||
#define XST_FR_TX_ERROR 1400
|
||||
#define XST_FR_TX_BUSY 1401
|
||||
#define XST_FR_BUF_LOCKED 1402
|
||||
#define XST_FR_NO_BUF 1403
|
||||
|
||||
/****************** USB constants 1410 - 1420 *******************************/
|
||||
|
||||
#define XST_USB_ALREADY_CONFIGURED 1410
|
||||
#define XST_USB_BUF_ALIGN_ERROR 1411
|
||||
#define XST_USB_NO_DESC_AVAILABLE 1412
|
||||
#define XST_USB_BUF_TOO_BIG 1413
|
||||
#define XST_USB_NO_BUF 1414
|
||||
|
||||
/****************** HWICAP constants 1421 - 1429 *****************************/
|
||||
|
||||
#define XST_HWICAP_WRITE_DONE 1421
|
||||
|
||||
|
||||
/****************** AXI VDMA constants 1430 - 1440 *****************************/
|
||||
|
||||
#define XST_VDMA_MISMATCH_ERROR 1430
|
||||
|
||||
/*********************** NAND Flash statuses 1441 - 1459 *********************/
|
||||
|
||||
#define XST_NAND_BUSY 1441L /* Flash is erasing or
|
||||
* programming
|
||||
*/
|
||||
#define XST_NAND_READY 1442L /* Flash is ready for commands
|
||||
*/
|
||||
#define XST_NAND_ERROR 1443L /* Flash had detected an
|
||||
* internal error.
|
||||
*/
|
||||
#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
|
||||
* driver
|
||||
*/
|
||||
#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
|
||||
*/
|
||||
#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
|
||||
* operation aborted due to a
|
||||
* timeout
|
||||
*/
|
||||
#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
|
||||
* addressible range
|
||||
*/
|
||||
#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
|
||||
*/
|
||||
#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
|
||||
* page of the device
|
||||
*/
|
||||
#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
|
||||
*/
|
||||
|
||||
#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
|
||||
*/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
typedef int XStatus;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
111
lib/bsp/standalone/src/cortexa53/xtime_l.c
Normal file
111
lib/bsp/standalone/src/cortexa53/xtime_l.c
Normal file
|
@ -0,0 +1,111 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xtime_l.c
|
||||
*
|
||||
* This file contains low level functions to get/set time from the Global Timer
|
||||
* register in the ARM Cortex A53 MP core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xtime_l.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Set the time in the Global Timer Counter Register.
|
||||
*
|
||||
* @param Value to be written to the Global Timer Counter Register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note In multiprocessor environment reference time will reset/lost for
|
||||
* all processors, when this function called by any one processor.
|
||||
*
|
||||
****************************************************************************/
|
||||
void XTime_SetTime(XTime Xtime_Global)
|
||||
{
|
||||
/*As the generic timer of A53 runs constantly time can not be set as desired
|
||||
so the API is left unimplemented*/
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Get the time from the Global Timer Counter Register.
|
||||
*
|
||||
* @param Pointer to the location to be updated with the time.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void XTime_GetTime(XTime *Xtime_Global)
|
||||
{
|
||||
*Xtime_Global = mfcp(CNTPCT_EL0);
|
||||
}
|
92
lib/bsp/standalone/src/cortexa53/xtime_l.h
Normal file
92
lib/bsp/standalone/src/cortexa53/xtime_l.h
Normal file
|
@ -0,0 +1,92 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law:
|
||||
* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
|
||||
* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
|
||||
* and
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage of
|
||||
* any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought
|
||||
* by a third party) even if such damage or loss was reasonably foreseeable
|
||||
* or Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or environmental
|
||||
* damage (individually and collectively, "Critical Applications").
|
||||
* Customer assumes the sole risk and liability of any use of Xilinx products in
|
||||
* Critical Applications, subject only to applicable laws and regulations
|
||||
* governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xtime_l.h
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- ---------------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* </pre>
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XTIME_H /* prevent circular inclusions */
|
||||
#define XTIME_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
typedef u64 XTime;
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/* Global Timer is always clocked at half of the CPU frequency */
|
||||
#define COUNTS_PER_SECOND 0x007A1200U
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void XTime_SetTime(XTime Xtime_Global);
|
||||
void XTime_GetTime(XTime *Xtime_Global);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XTIME_H */
|
0
lib/bsp/standalone/src/cortexa9/armcc/ARM_argv_veneer.c
Executable file → Normal file
0
lib/bsp/standalone/src/cortexa9/armcc/ARM_argv_veneer.c
Executable file → Normal file
6
lib/bsp/standalone/src/cortexa9/armcc/Makefile
Executable file → Normal file
6
lib/bsp/standalone/src/cortexa9/armcc/Makefile
Executable file → Normal file
|
@ -67,15 +67,15 @@ OBJECTS = $(OBJS)
|
|||
libs: boot_libs banner $(LIBS)
|
||||
|
||||
boot_libs:
|
||||
ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S)
|
||||
ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S)
|
||||
${COMPILER} $(INCLUDES) -E -o boot_post.s boot.S
|
||||
endif
|
||||
${AS} --cpu=Cortex-A9 --fpu=VFPv3_FP16 -o boot_post.o boot_post.s
|
||||
rm -f boot.S
|
||||
rm -f boot.S
|
||||
|
||||
$(AOBJS1): $(ASOURCES1)
|
||||
${AS} --cpu=Cortex-A9 --fpu=VFPv3_FP16 -o $@ $<
|
||||
|
||||
|
||||
$(AOBJS2): $(ASOURCES2)
|
||||
${AS} --cpu=Cortex-A9 --fpu=VFPv3_FP16 -o $@ $<
|
||||
|
||||
|
|
6
lib/bsp/standalone/src/cortexa9/armcc/_sys_close.c
Executable file → Normal file
6
lib/bsp/standalone/src/cortexa9/armcc/_sys_close.c
Executable file → Normal file
|
@ -1,6 +1,6 @@
|
|||
|
||||
// Stuv for close() sys-call
|
||||
__weak int _sys_close(int fh)
|
||||
#include "xil_types.h"
|
||||
/* Stuv for close() sys-call */
|
||||
__weak s32 _sys_close(s32 fh)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
|
10
lib/bsp/standalone/src/cortexa9/armcc/_sys_exit.c
Executable file → Normal file
10
lib/bsp/standalone/src/cortexa9/armcc/_sys_exit.c
Executable file → Normal file
|
@ -1,6 +1,8 @@
|
|||
|
||||
// Stuv for exit() sys-call
|
||||
__weak void _sys_exit(int rc)
|
||||
#include "xil_types.h"
|
||||
/* Stuv for exit() sys-call */
|
||||
__weak void _sys_exit(s32 rc)
|
||||
{
|
||||
while(1);
|
||||
while(1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
|
9
lib/bsp/standalone/src/cortexa9/armcc/_sys_iserror.c
Executable file → Normal file
9
lib/bsp/standalone/src/cortexa9/armcc/_sys_iserror.c
Executable file → Normal file
|
@ -1,9 +1,10 @@
|
|||
|
||||
// Stub for iserror() function
|
||||
__weak int _sys_iserror(int status)
|
||||
#include "xil_types.h"
|
||||
/* Stub for iserror() function */
|
||||
__weak s32 _sys_iserror(s32 status)
|
||||
{
|
||||
if(status<0)
|
||||
if(status<0) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
8
lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c
Executable file → Normal file
8
lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c
Executable file → Normal file
|
@ -1,7 +1,7 @@
|
|||
|
||||
// Stub for istty sys-call
|
||||
__weak int _sys_istty(unsigned int* f)
|
||||
{
|
||||
#include "xil_types.h"
|
||||
/* Stub for istty sys-call */
|
||||
__weak s32 _sys_istty(u32* f)
|
||||
{
|
||||
/* cannot read/write files */
|
||||
return 1;
|
||||
}
|
||||
|
|
6
lib/bsp/standalone/src/cortexa9/armcc/_sys_open.c
Executable file → Normal file
6
lib/bsp/standalone/src/cortexa9/armcc/_sys_open.c
Executable file → Normal file
|
@ -1,6 +1,6 @@
|
|||
|
||||
// Stub for open sys-call
|
||||
__weak int _sys_open(const char* name, int openmode)
|
||||
#include "xil_types.h"
|
||||
/* Stub for open sys-call */
|
||||
__weak s32 _sys_open(const char8* name, s32 openmode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
8
lib/bsp/standalone/src/cortexa9/armcc/_sys_read.c
Executable file → Normal file
8
lib/bsp/standalone/src/cortexa9/armcc/_sys_read.c
Executable file → Normal file
|
@ -1,7 +1,7 @@
|
|||
|
||||
// Stub for read() sys-call
|
||||
__weak int _sys_read(unsigned int fh, unsigned char *buf, unsigned int len, int mode)
|
||||
#include "xil_types.h"
|
||||
/* Stub for read() sys-call */
|
||||
__weak s32 _sys_read(u32 fh, u8 *buf, u32 len, s32 mode)
|
||||
{
|
||||
// Return the number of character NOT read
|
||||
/* Return the number of character NOT read */
|
||||
return len;
|
||||
}
|
||||
|
|
13
lib/bsp/standalone/src/cortexa9/armcc/_sys_write.c
Executable file → Normal file
13
lib/bsp/standalone/src/cortexa9/armcc/_sys_write.c
Executable file → Normal file
|
@ -1,15 +1,18 @@
|
|||
#include "xil_types.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
__weak int _sys_write(unsigned int fh, const unsigned char *buf, unsigned int len, int mode)
|
||||
__weak s32 _sys_write(u32 fh, const u8 *buf, u32 len, s32 mode)
|
||||
{
|
||||
#ifdef STDOUT_BASEADDRESS
|
||||
unsigned int volatile *uart_base = (unsigned int *)STDOUT_BASEADDRESS;
|
||||
int i;
|
||||
u32 volatile *uart_base = (u32 *)STDOUT_BASEADDRESS;
|
||||
s32 i;
|
||||
|
||||
for (i =0; i < len;i++) {
|
||||
/* wait if TNFUL */
|
||||
while (*(uart_base + 11) & (1 << 14)) ;
|
||||
*(uart_base + 12) = buf[i];
|
||||
while (*(uart_base + 11U) & (1U << 14U)) {
|
||||
;
|
||||
}
|
||||
*(uart_base + 12U) = buf[i];
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
|
|
71
lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s
Executable file → Normal file
71
lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s
Executable file → Normal file
|
@ -1,4 +1,3 @@
|
|||
;* $Id: asm_vectors.s,v 1.1.4.1 2011/10/24 09:35:17 sadanan Exp $
|
||||
;******************************************************************************
|
||||
;
|
||||
; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
|
@ -43,8 +42,8 @@
|
|||
; ----- ------- -------- ---------------------------------------------------
|
||||
; 1.00a ecm/sdm 10/20/09 Initial version
|
||||
; 3.11a asa 9/17/13 Added support for neon.
|
||||
; 4.00 pkp 01/22/14 Modified return addresses for interrupt
|
||||
; handlers
|
||||
; 4.00 pkp 01/22/14 Modified return addresses for interrupt
|
||||
; handlers
|
||||
;</pre>
|
||||
;
|
||||
; @note
|
||||
|
@ -79,8 +78,8 @@ _vector_table
|
|||
B FIQHandler
|
||||
|
||||
|
||||
IRQHandler ; IRQ vector handler
|
||||
|
||||
IRQHandler ; IRQ vector handler
|
||||
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
vpush {d0-d7}
|
||||
vpush {d16-d31}
|
||||
|
@ -95,12 +94,12 @@ IRQHandler ; IRQ vector handler
|
|||
vmsr FPSCR, r1
|
||||
vpop {d16-d31}
|
||||
vpop {d0-d7}
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
subs pc, lr, #4 ; adjust return
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
subs pc, lr, #4 ; adjust return
|
||||
|
||||
|
||||
FIQHandler ; FIQ vector handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
FIQHandler ; FIQ vector handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
vpush {d0-d7}
|
||||
vpush {d16-d31}
|
||||
vmrs r1, FPSCR
|
||||
|
@ -108,48 +107,48 @@ FIQHandler ; FIQ vector handler
|
|||
vmrs r1, FPEXC
|
||||
push {r1}
|
||||
FIQLoop
|
||||
bl FIQInterrupt ; FIQ vector
|
||||
bl FIQInterrupt ; FIQ vector
|
||||
pop {r1}
|
||||
vmsr FPEXC, r1
|
||||
pop {r1}
|
||||
vmsr FPSCR, r1
|
||||
vpop {d16-d31}
|
||||
vpop {d0-d7}
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
subs pc, lr, #4 ; adjust return
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
subs pc, lr, #4 ; adjust return
|
||||
|
||||
|
||||
Undefined ; Undefined handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
b _prestart
|
||||
Undefined ; Undefined handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
b _prestart
|
||||
|
||||
movs pc, lr
|
||||
|
||||
|
||||
SVCHandler ; SWI handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
tst r0, #0x20 ; check the T bit
|
||||
ldrneh r0, [lr,#-2] ; Thumb mode
|
||||
bicne r0, r0, #0xff00 ; Thumb mode
|
||||
ldreq r0, [lr,#-4] ; ARM mode
|
||||
biceq r0, r0, #0xff000000 ; ARM mode
|
||||
bl SWInterrupt ; SWInterrupt: call C function here
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
movs pc, lr ; adjust return
|
||||
SVCHandler ; SWI handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
tst r0, #0x20 ; check the T bit
|
||||
ldrneh r0, [lr,#-2] ; Thumb mode
|
||||
bicne r0, r0, #0xff00 ; Thumb mode
|
||||
ldreq r0, [lr,#-4] ; ARM mode
|
||||
biceq r0, r0, #0xff000000 ; ARM mode
|
||||
bl SWInterrupt ; SWInterrupt: call C function here
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
movs pc, lr ; adjust return
|
||||
|
||||
|
||||
DataAbortHandler ; Data Abort handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
subs pc, lr, #8 ; adjust return
|
||||
DataAbortHandler ; Data Abort handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
subs pc, lr, #8 ; adjust return
|
||||
|
||||
PrefetchAbortHandler ; Prefetch Abort handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
subs pc, lr, #4 ; adjust return
|
||||
PrefetchAbortHandler ; Prefetch Abort handler
|
||||
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
|
||||
bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
|
||||
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
|
||||
subs pc, lr, #4 ; adjust return
|
||||
|
||||
|
||||
END
|
||||
|
|
193
lib/bsp/standalone/src/cortexa9/armcc/boot.S
Executable file → Normal file
193
lib/bsp/standalone/src/cortexa9/armcc/boot.S
Executable file → Normal file
|
@ -1,4 +1,3 @@
|
|||
;* $Id: boot.S,v 1.1.4.1 2011/10/24 09:35:18 sadanan Exp $
|
||||
;******************************************************************************
|
||||
;
|
||||
; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
|
@ -43,7 +42,7 @@
|
|||
; ----- ------- -------- ---------------------------------------------------
|
||||
; 1.00a ecm/sdm 10/20/09 Initial version
|
||||
; 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
|
||||
; 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
|
||||
; 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
|
||||
; register settings.
|
||||
; 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
|
||||
; register settings.
|
||||
|
@ -100,27 +99,27 @@ SLCRlockKey EQU 0x767B /* SLCR lock key */
|
|||
SLCRUnlockKey EQU 0xDF0D /* SLCR unlock key */
|
||||
SLCRL2cRamConfig EQU 0x00020202 /* SLCR L2C ram configuration */
|
||||
|
||||
CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU
|
||||
CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000
|
||||
CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU
|
||||
CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000
|
||||
|
||||
L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable
|
||||
L2CCControl EQU 0x01 ; Enable L2CC
|
||||
L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM
|
||||
L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM
|
||||
L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable
|
||||
L2CCControl EQU 0x01 ; Enable L2CC
|
||||
L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM
|
||||
L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM
|
||||
|
||||
FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30)
|
||||
FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30)
|
||||
|
||||
AREA |.boot|, CODE
|
||||
PRESERVE8
|
||||
|
||||
|
||||
; this initializes the various processor modes
|
||||
; this initializes the various processor modes
|
||||
|
||||
_prestart
|
||||
_boot
|
||||
|
||||
#if XPAR_CPU_ID==0
|
||||
; only allow cp0 through
|
||||
; only allow cp0 through
|
||||
mrc p15,0,r1,c0,c0,5
|
||||
and r1, r1, #0xf
|
||||
cmp r1, #0
|
||||
|
@ -130,7 +129,7 @@ EndlessLoop0
|
|||
b EndlessLoop0
|
||||
|
||||
#elif XPAR_CPU_ID==1
|
||||
; only allow cp1 through
|
||||
; only allow cp1 through
|
||||
mrc p15,0,r1,c0,c0,5
|
||||
and r1, r1, #0xf
|
||||
cmp r1, #1
|
||||
|
@ -142,24 +141,24 @@ EndlessLoop1
|
|||
|
||||
OKToRun
|
||||
mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
|
||||
and r5, r0, #0x00f00000
|
||||
and r5, r0, #0x00f00000
|
||||
and r6, r0, #0x0000000f
|
||||
orr r6, r6, r5, lsr #20-4
|
||||
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_742230
|
||||
cmp r6, #0x22 /* only present up to r2p2 */
|
||||
mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
|
||||
orrle r10, r10, #1 << 4 /* set bit #4 */
|
||||
mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_743622
|
||||
teq r5, #0x00200000 /* only present in r2p* */
|
||||
mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
|
||||
orreq r10, r10, #1 << 6 /* set bit #6 */
|
||||
mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
|
||||
#endif
|
||||
|
||||
|
||||
/* set VBAR to the _vector_table address in scatter file */
|
||||
ldr r0, =_vector_table
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
|
@ -175,18 +174,18 @@ OKToRun
|
|||
ldr r6, =0xffff
|
||||
str r6, [r7]
|
||||
|
||||
; Write to ACTLR
|
||||
; Write to ACTLR
|
||||
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
|
||||
orr r0, r0, #(0x01 << 6) ; SMP bit
|
||||
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
|
||||
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
|
||||
mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
|
||||
|
||||
; Invalidate caches and TLBs
|
||||
mov r0,#0 ; r0 = 0
|
||||
mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
|
||||
mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
|
||||
mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
|
||||
bl invalidate_dcache ; invalidate dcache
|
||||
; Invalidate caches and TLBs
|
||||
mov r0,#0 ; r0 = 0
|
||||
mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
|
||||
mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
|
||||
mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
|
||||
bl invalidate_dcache ; invalidate dcache
|
||||
|
||||
; Invalidate L2c Cache
|
||||
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
|
||||
|
@ -216,21 +215,21 @@ OKToRun
|
|||
ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
|
||||
; Load L2CC base address base + sync register
|
||||
; poll for completion
|
||||
Sync
|
||||
Sync
|
||||
ldr r1, [r0]
|
||||
cmp r1, #0
|
||||
bne Sync
|
||||
|
||||
ldr r0,=L2CCIntRaw ; clear pending interrupts
|
||||
ldr r1,[r0]
|
||||
ldr r0,=L2CCIntClear
|
||||
ldr r0,=L2CCIntClear
|
||||
str r1,[r0]
|
||||
#endif
|
||||
|
||||
; Disable MMU, if enabled
|
||||
mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
|
||||
bic r0, r0, #0x1 ; clear bit 0
|
||||
mcr p15, 0, r0, c1, c0, 0 ; write value back
|
||||
; Disable MMU, if enabled
|
||||
mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
|
||||
bic r0, r0, #0x1 ; clear bit 0
|
||||
mcr p15, 0, r0, c1, c0, 0 ; write value back
|
||||
|
||||
#ifdef SHAREABLE_DDR
|
||||
; Mark the entire DDR memory as shareable
|
||||
|
@ -259,12 +258,12 @@ mmu_loop:
|
|||
bge mmu_loop ; loop till 512MB is covered
|
||||
#endif
|
||||
|
||||
mrs r0, cpsr ; get the current PSR
|
||||
mvn r1, #0x1f ; set up the irq stack pointer
|
||||
mrs r0, cpsr ; get the current PSR
|
||||
mvn r1, #0x1f ; set up the irq stack pointer
|
||||
and r2, r1, r0
|
||||
orr r2, r2, #0x12 ; IRQ mode
|
||||
orr r2, r2, #0x12 ; IRQ mode
|
||||
msr apsr, r2 ; was cpsr, apsr is considered synonym
|
||||
ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer
|
||||
ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer
|
||||
|
||||
mrs r0, cpsr ; get the current PSR
|
||||
mvn r1, #0x1f ; set up the supervisor stack pointer
|
||||
|
@ -280,43 +279,43 @@ mmu_loop:
|
|||
msr apsr, r2 ; was cpsr, apsr is considered synonym
|
||||
ldr r13,=|Image$$ABORT_STACK$$ZI$$Limit| ; Abort stack pointer
|
||||
|
||||
mrs r0, cpsr ; get the current PSR
|
||||
mvn r1, #0x1f ; set up the system stack pointer
|
||||
mrs r0, cpsr ; get the current PSR
|
||||
mvn r1, #0x1f ; set up the system stack pointer
|
||||
and r2, r1, r0
|
||||
orr r2, r2, #0x1f ; SYS mode
|
||||
orr r2, r2, #0x1f ; SYS mode
|
||||
msr apsr, r2 ; was cpsr, apsr is considered synonym
|
||||
ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer
|
||||
ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer
|
||||
|
||||
; enable MMU and cache
|
||||
; enable MMU and cache
|
||||
|
||||
ldr r0,=MMUTable ; Load MMU translation table base
|
||||
orr r0, r0, #0x5B ; Outer-cacheable, WB
|
||||
mcr p15, 0, r0, c2, c0, 0 ; TTB0
|
||||
|
||||
ldr r0,=MMUTable ; Load MMU translation table base
|
||||
orr r0, r0, #0x5B ; Outer-cacheable, WB
|
||||
mcr p15, 0, r0, c2, c0, 0 ; TTB0
|
||||
|
||||
mvn r0,#0
|
||||
mcr p15,0,r0,c3,c0,0
|
||||
|
||||
; Enable mmu, icahce and dcache
|
||||
ldr r0,=CRValMmuCac
|
||||
|
||||
mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU
|
||||
dsb ; dsb allow the MMU to start up
|
||||
isb ; isb flush prefetch buffer
|
||||
mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU
|
||||
dsb ; dsb allow the MMU to start up
|
||||
isb ; isb flush prefetch buffer
|
||||
|
||||
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
|
||||
#if USE_AMP!=1
|
||||
ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
|
||||
ldr r1,=SLCRUnlockKey /* set unlock key */
|
||||
str r1, [r0] /* Unlock SLCR */
|
||||
|
||||
|
||||
ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
|
||||
ldr r1,=SLCRL2cRamConfig /* set the configuration value */
|
||||
str r1, [r0] /* store the L2c Ram Control Register */
|
||||
|
||||
|
||||
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
|
||||
ldr r1,=SLCRlockKey /* set lock key */
|
||||
str r1, [r0] /* lock SLCR */
|
||||
|
||||
|
||||
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
|
||||
ldr r1,[r0] ; read the register
|
||||
mov r2, #L2CCControl ; set the enable bit
|
||||
|
@ -325,28 +324,28 @@ mmu_loop:
|
|||
#endif
|
||||
|
||||
mov r0, r0
|
||||
mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1
|
||||
orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11
|
||||
mcr p15, 0, r1, c1, c0, 2 ; write back into CACR
|
||||
mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1
|
||||
orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11
|
||||
mcr p15, 0, r1, c1, c0, 2 ; write back into CACR
|
||||
|
||||
; enable vfp
|
||||
fmrx r1, FPEXC ; read the exception register
|
||||
orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state
|
||||
fmxr FPEXC, r1 ; write back the exception register
|
||||
; enable vfp
|
||||
fmrx r1, FPEXC ; read the exception register
|
||||
orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state
|
||||
fmxr FPEXC, r1 ; write back the exception register
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable
|
||||
mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable
|
||||
orr r0, r0, #(0x01 << 11) ; #0x8000
|
||||
mcr p15,0,r0,c1,c0,0
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register
|
||||
orr r0, r0, #(0x1 << 2) ; enable Dside prefetch
|
||||
orr r0, r0, #(0x1 << 1) ; enable L2 prefetch
|
||||
mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register
|
||||
orr r0, r0, #(0x1 << 2) ; enable Dside prefetch
|
||||
orr r0, r0, #(0x1 << 1) ; enable L2 prefetch
|
||||
mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register
|
||||
|
||||
mrs r0, cpsr /* get the current PSR */
|
||||
bic r0, r0, #0x100 /* enable asynchronous abort exception */
|
||||
msr cpsr_xsf, r0
|
||||
|
||||
|
||||
; Clear cp15 regs with unknown reset values
|
||||
mov r0, #0x0
|
||||
mcr p15, 0, r0, c5, c0, 0 ; DFSR
|
||||
|
@ -358,19 +357,19 @@ mmu_loop:
|
|||
mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
|
||||
mcr p15, 5, r0, c15, c5, 2 ; Write Lockdown TLB VA
|
||||
|
||||
; Reset and start Cycle Counter
|
||||
mov r2, #0x80000000 ; clear overflow
|
||||
; Reset and start Cycle Counter
|
||||
mov r2, #0x80000000 ; clear overflow
|
||||
mcr p15, 0, r2, c9, c12, 3
|
||||
mov r2, #0xd ; D, C, E
|
||||
mov r2, #0xd ; D, C, E
|
||||
mcr p15, 0, r2, c9, c12, 0
|
||||
mov r2, #0x80000000 ; enable cycle counter
|
||||
mov r2, #0x80000000 ; enable cycle counter
|
||||
mcr p15, 0, r2, c9, c12, 1
|
||||
|
||||
; Reset and start Global Timer
|
||||
mov r0, #0x0
|
||||
mov r1, #0x0
|
||||
bl XTime_SetTime
|
||||
|
||||
|
||||
#ifdef PROFILING /* defined in Makefile */
|
||||
/* Setup profiling stuff */
|
||||
bl _profile_init
|
||||
|
@ -379,10 +378,10 @@ mmu_loop:
|
|||
; make sure argc and argv are valid
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
b __main ; jump to C startup code
|
||||
and r0, r0, r0 ; no op
|
||||
|
||||
Ldone b Ldone ; Paranoia: we should never get here
|
||||
b __main ; jump to C startup code
|
||||
and r0, r0, r0 ; no op
|
||||
|
||||
Ldone b Ldone ; Paranoia: we should never get here
|
||||
|
||||
|
||||
; *************************************************************************
|
||||
|
@ -393,47 +392,47 @@ Ldone b Ldone ; Paranoia: we should never get here
|
|||
; * the whole D-cache. Need to invalidate each line.
|
||||
; *
|
||||
; *************************************************************************
|
||||
|
||||
|
||||
invalidate_dcache
|
||||
mrc p15, 1, r0, c0, c0, 1 ; read CLIDR
|
||||
mrc p15, 1, r0, c0, c0, 1 ; read CLIDR
|
||||
ands r3, r0, #0x7000000
|
||||
mov r3, r3, lsr #23 ; cache level value (naturally aligned)
|
||||
mov r3, r3, lsr #23 ; cache level value (naturally aligned)
|
||||
beq finished
|
||||
mov r10, #0 ; start with level 0
|
||||
mov r10, #0 ; start with level 0
|
||||
loop1
|
||||
add r2, r10, r10, lsr #1 ; work out 3xcachelevel
|
||||
mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level
|
||||
and r1, r1, #7 ; get those 3 bits alone
|
||||
add r2, r10, r10, lsr #1 ; work out 3xcachelevel
|
||||
mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level
|
||||
and r1, r1, #7 ; get those 3 bits alone
|
||||
cmp r1, #2
|
||||
blt skip ; no cache or only instruction cache at this level
|
||||
mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
|
||||
isb ; isb to sync the change to the CacheSizeID reg
|
||||
mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register
|
||||
and r2, r1, #7 ; extract the line length field
|
||||
add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
||||
blt skip ; no cache or only instruction cache at this level
|
||||
mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
|
||||
isb ; isb to sync the change to the CacheSizeID reg
|
||||
mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register
|
||||
and r2, r1, #7 ; extract the line length field
|
||||
add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
||||
ldr r4, =0x3ff
|
||||
ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned)
|
||||
clz r5, r4 ; r5 is the bit position of the way size increment
|
||||
ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned)
|
||||
clz r5, r4 ; r5 is the bit position of the way size increment
|
||||
ldr r7, =0x7fff
|
||||
ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned)
|
||||
ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned)
|
||||
loop2
|
||||
mov r9, r4 ; r9 working copy of the max way size (right aligned)
|
||||
mov r9, r4 ; r9 working copy of the max way size (right aligned)
|
||||
loop3
|
||||
orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11
|
||||
orr r11, r11, r7, lsl r2 ; factor in the index number
|
||||
mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way
|
||||
subs r9, r9, #1 ; decrement the way number
|
||||
orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11
|
||||
orr r11, r11, r7, lsl r2 ; factor in the index number
|
||||
mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way
|
||||
subs r9, r9, #1 ; decrement the way number
|
||||
bge loop3
|
||||
subs r7, r7, #1 ; decrement the index
|
||||
subs r7, r7, #1 ; decrement the index
|
||||
bge loop2
|
||||
skip
|
||||
add r10, r10, #2 ; increment the cache number
|
||||
add r10, r10, #2 ; increment the cache number
|
||||
cmp r3, r10
|
||||
bgt loop1
|
||||
|
||||
finished
|
||||
mov r10, #0 ; swith back to cache level 0
|
||||
mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
|
||||
mov r10, #0 ; swith back to cache level 0
|
||||
mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
|
||||
isb
|
||||
|
||||
bx lr
|
||||
|
|
13
lib/bsp/standalone/src/cortexa9/armcc/translation_table.s
Executable file → Normal file
13
lib/bsp/standalone/src/cortexa9/armcc/translation_table.s
Executable file → Normal file
|
@ -1,4 +1,3 @@
|
|||
;* $Id: translation_table.s,v 1.1.4.1 2011/10/24 09:35:18 sadanan Exp $
|
||||
;******************************************************************************
|
||||
;
|
||||
; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
|
@ -68,11 +67,11 @@ MMUTable
|
|||
GBLA count
|
||||
GBLA sect
|
||||
|
||||
; 0x00000000 - 0x3ffffff (DDR Cacheable)
|
||||
; 0x00000000 - 0x3ffffff (DDR Cacheable)
|
||||
count SETA 0
|
||||
sect SETA 0
|
||||
WHILE count<0x400
|
||||
DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
|
||||
DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
WEND
|
||||
|
@ -96,7 +95,7 @@ count SETA count+1
|
|||
; 0xc0000000 - 0xdfffffff (undef)
|
||||
count SETA 0
|
||||
WHILE count<0x200
|
||||
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
|
||||
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
WEND
|
||||
|
@ -104,7 +103,7 @@ count SETA count+1
|
|||
; 0xe0000000 - 0xe02fffff (IOP dev)
|
||||
count SETA 0
|
||||
WHILE count<0x3
|
||||
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
|
||||
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
WEND
|
||||
|
@ -112,7 +111,7 @@ count SETA count+1
|
|||
; 0xe0300000 - 0xe0ffffff (undef/reserved)
|
||||
count SETA 0
|
||||
WHILE count<0xD
|
||||
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
|
||||
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
WEND
|
||||
|
@ -144,7 +143,7 @@ count SETA count+1
|
|||
; 0xe6000000 - 0xf7ffffff (reserved)
|
||||
count SETA 0
|
||||
WHILE count<0x120
|
||||
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
|
||||
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
WEND
|
||||
|
|
12
lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.c
Executable file → Normal file
12
lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.c
Executable file → Normal file
|
@ -109,38 +109,38 @@ __asm void dmb(void)
|
|||
}
|
||||
|
||||
/* Memory Operations */
|
||||
__asm unsigned int ldr(unsigned int adr)
|
||||
__asm u32 ldr(u32 adr)
|
||||
{
|
||||
ldr r0, [r0]
|
||||
bx lr
|
||||
}
|
||||
|
||||
__asm unsigned int ldrb(unsigned int adr)
|
||||
__asm u32 ldrb(u32 adr)
|
||||
{
|
||||
ldrb r0, [r0]
|
||||
bx lr
|
||||
}
|
||||
|
||||
__asm void str(unsigned int adr, unsigned int val)
|
||||
__asm void str(u32 adr, u32 val)
|
||||
{
|
||||
str r1, [r0]
|
||||
bx lr
|
||||
}
|
||||
|
||||
__asm void strb(unsigned int adr, unsigned int val)
|
||||
__asm void strb(u32 adr, u32 val)
|
||||
{
|
||||
strb r1, [r0]
|
||||
bx lr
|
||||
}
|
||||
|
||||
/* Count leading zeroes (clz) */
|
||||
__asm unsigned int clz(unsigned int arg)
|
||||
__asm u32 clz(u32 arg)
|
||||
{
|
||||
clz r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
__asm unsigned int mfcpsr(void)
|
||||
__asm u32 mfcpsr(void)
|
||||
{
|
||||
mrs r0, cpsr
|
||||
bx lr
|
||||
|
|
20
lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.h
Executable file → Normal file
20
lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.h
Executable file → Normal file
|
@ -51,7 +51,7 @@
|
|||
#define XPSEUDO_ASM_RVCT_H /* by using protection macros */
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
@ -67,7 +67,7 @@ extern "C" {
|
|||
#define tostring(s) #s
|
||||
|
||||
|
||||
#define mtcpsr(v) { volatile register unsigned int Reg __asm("cpsr");\
|
||||
#define mtcpsr(v) { volatile register u32 Reg __asm("cpsr");\
|
||||
Reg = v; }
|
||||
|
||||
/* general purpose register read/write */
|
||||
|
@ -76,7 +76,7 @@ extern "C" {
|
|||
val = Reg; \
|
||||
val;})*/
|
||||
|
||||
#define mtgpr(rn, v) { volatile register unsigned int Reg __asm("r" stringify(rn));\
|
||||
#define mtgpr(rn, v) { volatile register u32 Reg __asm("r" stringify(rn));\
|
||||
Reg = v; }
|
||||
|
||||
/* CP15 operations */
|
||||
|
@ -84,7 +84,7 @@ extern "C" {
|
|||
val = register unsigned int Reg __asm(rn); \
|
||||
val;})*/
|
||||
|
||||
#define mtcp(rn, v) { volatile register unsigned int Reg __asm(rn); \
|
||||
#define mtcp(rn, v) { volatile register u32 Reg __asm(rn); \
|
||||
Reg = v; }
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
|
@ -111,17 +111,17 @@ __asm void dsb(void);
|
|||
__asm void dmb(void);
|
||||
|
||||
/* Memory Operations */
|
||||
__asm unsigned int ldr(unsigned int adr);
|
||||
__asm u32 ldr(u32 adr);
|
||||
|
||||
__asm unsigned int ldrb(unsigned int adr);
|
||||
__asm u32 ldrb(u32 adr);
|
||||
|
||||
__asm void str(unsigned int adr, unsigned int val);
|
||||
__asm void str(u32 adr, u32 val);
|
||||
|
||||
__asm void strb(unsigned int adr, unsigned int val);
|
||||
__asm void strb(u32 adr, u32 val);
|
||||
|
||||
/* Count leading zeroes (clz) */
|
||||
__asm unsigned int clz(unsigned int arg);
|
||||
__asm unsigned int mfcpsr(void);
|
||||
__asm u32 clz(u32 arg);
|
||||
__asm u32 mfcpsr(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
3
lib/bsp/standalone/src/cortexa9/gcc/Makefile
Executable file → Normal file
3
lib/bsp/standalone/src/cortexa9/gcc/Makefile
Executable file → Normal file
|
@ -67,7 +67,7 @@ libs: $(LIBS)
|
|||
standalone_libs: $(LIBSOURCES)
|
||||
echo "Compiling standalone"
|
||||
$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
|
||||
profile_libs:
|
||||
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" libs
|
||||
|
@ -84,4 +84,3 @@ profile_includes:
|
|||
clean:
|
||||
rm -rf ${OUTS}
|
||||
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean
|
||||
|
||||
|
|
7
lib/bsp/standalone/src/cortexa9/gcc/_exit.c
Executable file → Normal file
7
lib/bsp/standalone/src/cortexa9/gcc/_exit.c
Executable file → Normal file
|
@ -31,11 +31,14 @@
|
|||
******************************************************************************/
|
||||
|
||||
#include <unistd.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
/* _exit - Simple implementation. Does not return.
|
||||
*/
|
||||
__attribute__((weak)) void _exit (int status)
|
||||
__attribute__((weak)) void _exit (sint32 status)
|
||||
{
|
||||
(void)status;
|
||||
while (1);
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
|
7
lib/bsp/standalone/src/cortexa9/gcc/_open.c
Executable file → Normal file
7
lib/bsp/standalone/src/cortexa9/gcc/_open.c
Executable file → Normal file
|
@ -31,10 +31,11 @@
|
|||
******************************************************************************/
|
||||
|
||||
#include <errno.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) int _open(const char *buf, int flags, int mode);
|
||||
__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -42,9 +43,9 @@ extern "C" {
|
|||
* _open -- open a file descriptor. We don't have a filesystem, so
|
||||
* we return an error.
|
||||
*/
|
||||
__attribute__((weak)) int _open(const char *buf, int flags, int mode)
|
||||
__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
|
||||
{
|
||||
(void)buf;
|
||||
(void *)buf;
|
||||
(void)flags;
|
||||
(void)mode;
|
||||
errno = EIO;
|
||||
|
|
30
lib/bsp/standalone/src/cortexa9/gcc/_sbrk.c
Executable file → Normal file
30
lib/bsp/standalone/src/cortexa9/gcc/_sbrk.c
Executable file → Normal file
|
@ -31,31 +31,41 @@
|
|||
******************************************************************************/
|
||||
|
||||
#include <sys/types.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
extern int _heap_start;
|
||||
extern int _heap_end;
|
||||
extern u8 _heap_start[];
|
||||
extern u8 _heap_end[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) caddr_t _sbrk ( int incr );
|
||||
__attribute__((weak)) caddr_t _sbrk ( s32 incr );
|
||||
}
|
||||
#endif
|
||||
|
||||
__attribute__((weak)) caddr_t _sbrk ( int incr )
|
||||
__attribute__((weak)) caddr_t _sbrk ( s32 incr )
|
||||
{
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
static u8 *heap = NULL;
|
||||
u8 *prev_heap;
|
||||
static u8 *HeapEndPtr = (u8 *)&_heap_end;
|
||||
caddr_t Status;
|
||||
|
||||
if (heap == NULL) {
|
||||
heap = (unsigned char *)&_heap_start;
|
||||
heap = (u8 *)&_heap_start;
|
||||
}
|
||||
prev_heap = heap;
|
||||
|
||||
heap += incr;
|
||||
|
||||
if ((unsigned)heap > (unsigned)&_heap_end){
|
||||
return (caddr_t) -1;
|
||||
if (heap > HeapEndPtr){
|
||||
Status = (caddr_t) -1;
|
||||
}
|
||||
return (caddr_t) prev_heap;
|
||||
else if (prev_heap != NULL) {
|
||||
Status = (caddr_t) ((void *)prev_heap);
|
||||
}
|
||||
else {
|
||||
Status = (caddr_t) -1;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
|
0
lib/bsp/standalone/src/cortexa9/gcc/abort.c
Executable file → Normal file
0
lib/bsp/standalone/src/cortexa9/gcc/abort.c
Executable file → Normal file
10
lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S
Executable file → Normal file
10
lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S
Executable file → Normal file
|
@ -44,7 +44,7 @@
|
|||
* 3.05a sdm 02/02/12 Save lr when profiling is enabled
|
||||
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
|
||||
* 'xil_errata.h' for errata description
|
||||
* 4.00a pkp 22/01/14 Modified return addresses for interrupt
|
||||
* 4.00a pkp 22/01/14 Modified return addresses for interrupt
|
||||
* handlers (DataAbortHandler and SVCHandler)
|
||||
* to fix CR#767251
|
||||
* </pre>
|
||||
|
@ -86,7 +86,7 @@ _vector_table:
|
|||
|
||||
|
||||
IRQHandler: /* IRQ vector handler */
|
||||
|
||||
|
||||
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
|
||||
#ifdef __ARM_NEON__
|
||||
vpush {d0-d7}
|
||||
|
@ -104,7 +104,7 @@ IRQHandler: /* IRQ vector handler */
|
|||
#endif
|
||||
|
||||
bl IRQInterrupt /* IRQ vector */
|
||||
|
||||
|
||||
#ifdef __ARM_NEON__
|
||||
pop {r1}
|
||||
vmsr FPEXC, r1
|
||||
|
@ -114,7 +114,7 @@ IRQHandler: /* IRQ vector handler */
|
|||
vpop {d0-d7}
|
||||
#endif
|
||||
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
|
||||
|
||||
|
||||
|
||||
subs pc, lr, #4 /* adjust return */
|
||||
|
||||
|
@ -150,7 +150,7 @@ Undefined: /* Undefined handler */
|
|||
|
||||
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
|
||||
|
||||
b _prestart
|
||||
b _prestart
|
||||
|
||||
movs pc, lr
|
||||
|
||||
|
|
36
lib/bsp/standalone/src/cortexa9/gcc/boot.S
Executable file → Normal file
36
lib/bsp/standalone/src/cortexa9/gcc/boot.S
Executable file → Normal file
|
@ -41,16 +41,16 @@
|
|||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 1.00a ecm/sdm 10/20/09 Initial version
|
||||
* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
|
||||
* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
|
||||
* register settings.
|
||||
* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
|
||||
* register settings.
|
||||
* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
|
||||
* performance. Changed the property of the ".boot"
|
||||
* section.
|
||||
* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
|
||||
* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
|
||||
* Register settings
|
||||
* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
|
||||
* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
|
||||
* value of 0x00020202. Fix for CR 697094 (SI#687034).
|
||||
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
|
||||
* 'xil_errata.h' for errata description
|
||||
|
@ -99,13 +99,13 @@
|
|||
/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
|
||||
.if SIM_MODE == 1
|
||||
.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
|
||||
.else
|
||||
.else
|
||||
.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
|
||||
.endif
|
||||
|
||||
.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
|
||||
|
||||
.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
|
||||
.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
|
||||
Event monitor bus enable and Way Size (64 KB) */
|
||||
.set L2CCControl, 0x01 /* Enable L2CC */
|
||||
.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
|
||||
|
@ -158,7 +158,7 @@ EndlessLoop1:
|
|||
|
||||
OKToRun:
|
||||
mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
|
||||
and r5, r0, #0x00f00000
|
||||
and r5, r0, #0x00f00000
|
||||
and r6, r0, #0x0000000f
|
||||
orr r6, r6, r5, lsr #20-4
|
||||
|
||||
|
@ -183,7 +183,7 @@ OKToRun:
|
|||
/*set scu enable bit in scu*/
|
||||
ldr r7, =0xf8f00000
|
||||
ldr r0, [r7]
|
||||
orr r0, r0, #0x1
|
||||
orr r0, r0, #0x1
|
||||
str r0, [r7]
|
||||
|
||||
/*invalidate scu*/
|
||||
|
@ -194,7 +194,7 @@ OKToRun:
|
|||
/* Write to ACTLR */
|
||||
mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
|
||||
orr r0, r0, #(0x01 << 6) /* set SMP bit */
|
||||
orr r0, r0, #(0x01 ) /* */
|
||||
orr r0, r0, #(0x01 ) /* */
|
||||
mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
|
||||
|
||||
/* Invalidate caches and TLBs */
|
||||
|
@ -238,7 +238,7 @@ Sync: ldr r1, [r0]
|
|||
|
||||
ldr r0,=L2CCIntRaw /* clear pending interrupts */
|
||||
ldr r1,[r0]
|
||||
ldr r0,=L2CCIntClear
|
||||
ldr r0,=L2CCIntClear
|
||||
str r1,[r0]
|
||||
#endif
|
||||
|
||||
|
@ -321,8 +321,8 @@ mmu_loop:
|
|||
ldr r0,=TblBase /* Load MMU translation table base */
|
||||
orr r0, r0, #0x5B /* Outer-cacheable, WB */
|
||||
mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
|
||||
|
||||
|
||||
|
||||
|
||||
mvn r0,#0 /* Load MMU domains -- all ones=manager */
|
||||
mcr p15,0,r0,c3,c0,0
|
||||
|
||||
|
@ -340,11 +340,11 @@ mmu_loop:
|
|||
ldr r1,=SLCRUnlockKey /* set unlock key */
|
||||
str r1, [r0] /* Unlock SLCR */
|
||||
|
||||
ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
|
||||
ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
|
||||
ldr r1,=SLCRL2cRamConfig /* set the configuration value */
|
||||
str r1, [r0] /* store the L2c Ram Control Register */
|
||||
|
||||
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
|
||||
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
|
||||
ldr r1,=SLCRlockKey /* set lock key */
|
||||
str r1, [r0] /* lock SLCR */
|
||||
|
||||
|
@ -366,7 +366,7 @@ mmu_loop:
|
|||
fmxr FPEXC, r1 /* write back the exception register */
|
||||
|
||||
mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
|
||||
orr r0, r0, #(0x01 << 11) /* #0x8000 */
|
||||
orr r0, r0, #(0x01 << 11) /* #0x8000 */
|
||||
mcr p15,0,r0,c1,c0,0
|
||||
|
||||
mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
|
||||
|
@ -377,11 +377,11 @@ mmu_loop:
|
|||
mrs r0, cpsr /* get the current PSR */
|
||||
bic r0, r0, #0x100 /* enable asynchronous abort exception */
|
||||
msr cpsr_xsf, r0
|
||||
|
||||
|
||||
|
||||
|
||||
b _start /* jump to C startup code */
|
||||
and r0, r0, r0 /* no op */
|
||||
|
||||
|
||||
.Ldone: b .Ldone /* Paranoia: we should never get here */
|
||||
|
||||
|
||||
|
@ -441,5 +441,3 @@ finished:
|
|||
bx lr
|
||||
|
||||
.end
|
||||
|
||||
|
||||
|
|
5
lib/bsp/standalone/src/cortexa9/gcc/close.c
Executable file → Normal file
5
lib/bsp/standalone/src/cortexa9/gcc/close.c
Executable file → Normal file
|
@ -29,9 +29,10 @@
|
|||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
#include "xil_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) int _close(int fd);
|
||||
__attribute__((weak)) s32 _close(s32 fd);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -39,7 +40,7 @@ extern "C" {
|
|||
* close -- We don't need to do anything, but pretend we did.
|
||||
*/
|
||||
|
||||
__attribute__((weak)) int _close(int fd)
|
||||
__attribute__((weak)) s32 _close(s32 fd)
|
||||
{
|
||||
(void)fd;
|
||||
return (0);
|
||||
|
|
2
lib/bsp/standalone/src/cortexa9/gcc/cpu_init.S
Executable file → Normal file
2
lib/bsp/standalone/src/cortexa9/gcc/cpu_init.S
Executable file → Normal file
|
@ -52,7 +52,7 @@
|
|||
|
||||
.text
|
||||
.global __cpu_init
|
||||
.align 2
|
||||
.align 2
|
||||
__cpu_init:
|
||||
|
||||
/* Clear cp15 regs with unknown reset values */
|
||||
|
|
7
lib/bsp/standalone/src/cortexa9/gcc/errno.c
Executable file → Normal file
7
lib/bsp/standalone/src/cortexa9/gcc/errno.c
Executable file → Normal file
|
@ -36,15 +36,16 @@
|
|||
|
||||
#include <errno.h>
|
||||
#include <reent.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) int * __errno ();
|
||||
__attribute__((weak)) sint32 * __errno (void);
|
||||
}
|
||||
#endif
|
||||
|
||||
__attribute__((weak)) int *
|
||||
__errno ()
|
||||
__attribute__((weak)) sint32 *
|
||||
__errno (void)
|
||||
{
|
||||
return &_REENT->_errno;
|
||||
}
|
||||
|
|
3
lib/bsp/standalone/src/cortexa9/gcc/fcntl.c
Executable file → Normal file
3
lib/bsp/standalone/src/cortexa9/gcc/fcntl.c
Executable file → Normal file
|
@ -31,12 +31,13 @@
|
|||
******************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
/*
|
||||
* fcntl -- Manipulate a file descriptor.
|
||||
* We don't have a filesystem, so we do nothing.
|
||||
*/
|
||||
__attribute__((weak)) int fcntl (int fd, int cmd, long arg)
|
||||
__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
|
||||
{
|
||||
(void)fd;
|
||||
(void)cmd;
|
||||
|
|
5
lib/bsp/standalone/src/cortexa9/gcc/fstat.c
Executable file → Normal file
5
lib/bsp/standalone/src/cortexa9/gcc/fstat.c
Executable file → Normal file
|
@ -31,16 +31,17 @@
|
|||
******************************************************************************/
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) int _fstat(int fd, struct stat *buf);
|
||||
__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* fstat -- Since we have no file system, we just return an error.
|
||||
*/
|
||||
__attribute__((weak)) int _fstat(int fd, struct stat *buf)
|
||||
__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
|
||||
{
|
||||
(void)fd;
|
||||
buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
|
||||
|
|
7
lib/bsp/standalone/src/cortexa9/gcc/getpid.c
Executable file → Normal file
7
lib/bsp/standalone/src/cortexa9/gcc/getpid.c
Executable file → Normal file
|
@ -30,21 +30,22 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
/*
|
||||
* getpid -- only one process, so just return 1.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) int _getpid();
|
||||
__attribute__((weak)) s32 _getpid(void);
|
||||
}
|
||||
#endif
|
||||
|
||||
__attribute__((weak)) int getpid()
|
||||
__attribute__((weak)) s32 getpid(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _getpid()
|
||||
__attribute__((weak)) s32 _getpid(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
|
7
lib/bsp/standalone/src/cortexa9/gcc/isatty.c
Executable file → Normal file
7
lib/bsp/standalone/src/cortexa9/gcc/isatty.c
Executable file → Normal file
|
@ -30,10 +30,11 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
#include <unistd.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) int _isatty(int fd);
|
||||
__attribute__((weak)) sint32 _isatty(sint32 fd);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -42,13 +43,13 @@ extern "C" {
|
|||
* returns 0 if not. Since we're hooked up to a
|
||||
* serial port, we'll say yes _AND return a 1.
|
||||
*/
|
||||
__attribute__((weak)) int isatty(int fd)
|
||||
__attribute__((weak)) sint32 isatty(sint32 fd)
|
||||
{
|
||||
(void)fd;
|
||||
return (1);
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _isatty(int fd)
|
||||
__attribute__((weak)) sint32 _isatty(sint32 fd)
|
||||
{
|
||||
(void)fd;
|
||||
return (1);
|
||||
|
|
13
lib/bsp/standalone/src/cortexa9/gcc/kill.c
Executable file → Normal file
13
lib/bsp/standalone/src/cortexa9/gcc/kill.c
Executable file → Normal file
|
@ -31,10 +31,11 @@
|
|||
******************************************************************************/
|
||||
#include <signal.h>
|
||||
#include <unistd.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) int _kill(int pid, int sig);
|
||||
__attribute__((weak)) s32 _kill(s32 pid, s32 sig);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -42,17 +43,19 @@ extern "C" {
|
|||
* kill -- go out via exit...
|
||||
*/
|
||||
|
||||
__attribute__((weak)) int kill(int pid, int sig)
|
||||
__attribute__((weak)) s32 kill(s32 pid, s32 sig)
|
||||
{
|
||||
if(pid == 1)
|
||||
if(pid == 1) {
|
||||
_exit(sig);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _kill(int pid, int sig)
|
||||
__attribute__((weak)) s32 _kill(s32 pid, s32 sig)
|
||||
{
|
||||
if(pid == 1)
|
||||
if(pid == 1) {
|
||||
_exit(sig);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
7
lib/bsp/standalone/src/cortexa9/gcc/lseek.c
Executable file → Normal file
7
lib/bsp/standalone/src/cortexa9/gcc/lseek.c
Executable file → Normal file
|
@ -32,16 +32,17 @@
|
|||
|
||||
#include <sys/types.h>
|
||||
#include <errno.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) off_t _lseek(int fd, off_t offset, int whence);
|
||||
__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* lseek -- Since a serial port is non-seekable, we return an error.
|
||||
*/
|
||||
__attribute__((weak)) off_t lseek(int fd, off_t offset, int whence)
|
||||
__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
|
||||
{
|
||||
(void)fd;
|
||||
(void)offset;
|
||||
|
@ -50,7 +51,7 @@ __attribute__((weak)) off_t lseek(int fd, off_t offset, int whence)
|
|||
return ((off_t)-1);
|
||||
}
|
||||
|
||||
__attribute__((weak)) off_t _lseek(int fd, off_t offset, int whence)
|
||||
__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
|
||||
{
|
||||
(void)fd;
|
||||
(void)offset;
|
||||
|
|
7
lib/bsp/standalone/src/cortexa9/gcc/open.c
Executable file → Normal file
7
lib/bsp/standalone/src/cortexa9/gcc/open.c
Executable file → Normal file
|
@ -31,19 +31,20 @@
|
|||
******************************************************************************/
|
||||
|
||||
#include <errno.h>
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) int open(const char *buf, int flags, int mode);
|
||||
__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* open -- open a file descriptor. We don't have a filesystem, so
|
||||
* we return an error.
|
||||
*/
|
||||
__attribute__((weak)) int open(const char *buf, int flags, int mode)
|
||||
__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
|
||||
{
|
||||
(void)buf;
|
||||
(void *)buf;
|
||||
(void)flags;
|
||||
(void)mode;
|
||||
errno = EIO;
|
||||
|
|
58
lib/bsp/standalone/src/cortexa9/gcc/read.c
Executable file → Normal file
58
lib/bsp/standalone/src/cortexa9/gcc/read.c
Executable file → Normal file
|
@ -33,12 +33,12 @@
|
|||
/* read.c -- read bytes from a input device.
|
||||
*/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xil_printf.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
__attribute__((weak)) int _read (int fd, char* buf, int nbytes);
|
||||
__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -46,23 +46,30 @@ extern "C" {
|
|||
* read -- read bytes from the serial port. Ignore fd, since
|
||||
* we only have stdin.
|
||||
*/
|
||||
__attribute__((weak)) int
|
||||
read (int fd, char* buf, int nbytes)
|
||||
__attribute__((weak)) s32
|
||||
read (s32 fd, char8* buf, s32 nbytes)
|
||||
{
|
||||
#ifdef STDIN_BASEADDRESS
|
||||
int i = 0;
|
||||
s32 i;
|
||||
char8* LocalBuf = buf;
|
||||
|
||||
(void)fd;
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
*(buf + i) = inbyte();
|
||||
if ((*(buf + i) == '\n' || *(buf + i) == '\r'))
|
||||
{
|
||||
i++;
|
||||
break;
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf += i;
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
*LocalBuf = inbyte();
|
||||
if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf -= i;
|
||||
}
|
||||
}
|
||||
|
||||
return (i);
|
||||
return (i + 1);
|
||||
#else
|
||||
(void)fd;
|
||||
(void)buf;
|
||||
|
@ -71,23 +78,30 @@ read (int fd, char* buf, int nbytes)
|
|||
#endif
|
||||
}
|
||||
|
||||
__attribute__((weak)) int
|
||||
_read (int fd, char* buf, int nbytes)
|
||||
__attribute__((weak)) s32
|
||||
_read (s32 fd, char8* buf, s32 nbytes)
|
||||
{
|
||||
#ifdef STDIN_BASEADDRESS
|
||||
int i = 0;
|
||||
s32 i;
|
||||
char8* LocalBuf = buf;
|
||||
|
||||
(void)fd;
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
*(buf + i) = inbyte();
|
||||
if ((*(buf + i) == '\n' || *(buf + i) == '\r'))
|
||||
{
|
||||
i++;
|
||||
break;
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf += i;
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
*LocalBuf = inbyte();
|
||||
if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(LocalBuf != NULL) {
|
||||
LocalBuf -= i;
|
||||
}
|
||||
}
|
||||
|
||||
return (i);
|
||||
return (i + 1);
|
||||
#else
|
||||
(void)fd;
|
||||
(void)buf;
|
||||
|
|
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Add table
Reference in a new issue