3f6f63b07e
This patch unifies standalone for both Zynq and ZynqMP platforms. Also follows misrac guidelines. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
171 lines
5.5 KiB
C
171 lines
5.5 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* This file contains confidential and proprietary information of Xilinx, Inc.
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* and is protected under U.S. and international copyright and other
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* intellectual property laws.
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*
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* DISCLAIMER
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* This disclaimer is not a license and does not grant any rights to the
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* materials distributed herewith. Except as otherwise provided in a valid
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* license issued to you by Xilinx, and to the maximum extent permitted by
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* applicable law:
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* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
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* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
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* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
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* and
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* (2) Xilinx shall not be liable (whether in contract or tort, including
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* negligence, or under any other theory of liability) for any loss or damage of
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* any kind or nature related to, arising under or in connection with these
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* materials, including for any direct, or any indirect, special, incidental,
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* or consequential loss or damage (including loss of data, profits, goodwill,
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* or any type of loss or damage suffered as a result of any action brought
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* by a third party) even if such damage or loss was reasonably foreseeable
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* or Xilinx had been advised of the possibility of the same.
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*
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* CRITICAL APPLICATIONS
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* Xilinx products are not designed or intended to be fail-safe, or for use in
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* any application requiring fail-safe performance, such as life-support or
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* safety devices or systems, Class III medical devices, nuclear facilities,
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* applications related to the deployment of airbags, or any other applications
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* that could lead to death, personal injury, or severe property or environmental
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* damage (individually and collectively, "Critical Applications").
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* Customer assumes the sole risk and liability of any use of Xilinx products in
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* Critical Applications, subject only to applicable laws and regulations
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* governing limitations on product liability.
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*
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* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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* AT ALL TIMES.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file uart.c
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*
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* This file contains APIs for configuring the UART.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 5.00 pkp 02/20/14 First release
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* </pre>
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*
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* @note
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*
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* None.
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*
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******************************************************************************/
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#include "xil_types.h"
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#include "xparameters.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/* Register offsets */
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#define UART_CR_OFFSET 0x00000000U
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#define UART_MR_OFFSET 0x00000004U
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#define UART_BAUDGEN_OFFSET 0x00000018U
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#define UART_BAUDDIV_OFFSET 0x00000034U
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#define MAX_BAUD_ERROR_RATE 0x00000003U /* max % error allowed */
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#define UART_BAUDRATE 115200U
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#define CSU_VERSION_REG 0xFFCA0044U
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void Init_Uart(void);
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void Init_Uart(void)
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{
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#ifdef STDOUT_BASEADDRESS
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u8 IterBAUDDIV; /* Iterator for available baud divisor values */
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u32 BRGR_Value; /* Calculated value for baud rate generator */
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u32 CalcBaudRate; /* Calculated baud rate */
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u32 BaudError; /* Diff between calculated and requested baud rate */
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u32 Best_BRGR = 0U; /* Best value for baud rate generator */
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u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
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u32 Best_Error = 0xFFFFFFFFU;
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u32 PercentError;
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u32 InputClk;
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u32 BaudRate = UART_BAUDRATE;
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#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
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InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
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#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
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InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
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#else
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/* STDIO is not set or axi_uart is being used for STDIO */
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return;
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#endif
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InputClk = 25000000U;
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/*
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* Determine the Baud divider. It can be 4to 254.
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* Loop through all possible combinations
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*/
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for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) {
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/*
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* Calculate the value for BRGR register
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*/
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BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 0x00000001U));
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/*
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* Calculate the baud rate from the BRGR value
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*/
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CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 0x00000001U));
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/*
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* Avoid unsigned integer underflow
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*/
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if (BaudRate > CalcBaudRate) {
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BaudError = BaudRate - CalcBaudRate;
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} else {
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BaudError = CalcBaudRate - BaudRate;
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}
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/*
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* Find the calculated baud rate closest to requested baud rate.
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*/
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if (Best_Error > BaudError) {
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Best_BRGR = BRGR_Value;
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Best_BAUDDIV = IterBAUDDIV;
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Best_Error = BaudError;
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}
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}
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/*
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* Make sure the best error is not too large.
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*/
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PercentError = (Best_Error * 100U) / BaudRate;
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if (MAX_BAUD_ERROR_RATE < PercentError) {
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return;
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}
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/* set CD and BDIV */
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV);
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/*
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* Veloce specific code
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*/
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if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) {
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 0x00000002U);
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 0x00000004U);
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}
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/*
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* 8 data, 1 stop, 0 parity bits
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* sel_clk=uart_clk=APB clock
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*/
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Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U);
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/* enable Tx/Rx and reset Tx/Rx data path */
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Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U);
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return;
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#endif
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}
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