Xilinx Embedded Software (embeddedsw) Development
![]() Previously, the PHY status for all lanes was being checked. This results in the driver thinking that the PHY never comes out of reset if the core is limited to a maximum lane count of 1 or 2 at the time the core is initialized. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com> |
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lib | ||
ThirdParty/sw_services/lwip140_v2_4 | ||
XilinxProcessorIPLib/drivers |