stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

dptx: Waiting for the PHY to come out of reset based on lane count.

Browse source 
Previously, the PHY status for all lanes was being checked. This results in the
driver thinking that the PHY never comes out of reset if the core is limited to
a maximum lane count of 1 or 2 at the time the core is initialized.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-01-07 12:26:50 -08:00 • committed by Suneel Garapati
parent f852cf5805
commit 3f97b78bf9
1 changed files with 10 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
XilinxProcessorIPLib/drivers/dptx/src/xdptx.c
View file

@ -2640,12 +2640,19 @@ static u32 XDptx_WaitPhyReady(XDptx *InstancePtr)
{
u32 Timeout = 100;
u32 PhyStatus;
u32 Mask;
if (InstancePtr->Config.MaxLaneCount > 2) {
Mask = XDPTX_PHY_STATUS_ALL_LANES_READY_MASK;
}
else {
Mask = XDPTX_PHY_STATUS_LANES_0_1_READY_MASK;
}
/* Wait until the PHY is ready. */
do {
PhyStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_PHY_STATUS) &
XDPTX_PHY_STATUS_ALL_LANES_READY_MASK;
XDPTX_PHY_STATUS) & Mask;
/* Protect against an infinite loop. */
if (!Timeout--) {
@ -2653,7 +2660,7 @@ static u32 XDptx_WaitPhyReady(XDptx *InstancePtr)
}
XDptx_WaitUs(InstancePtr, 20);
}
while (PhyStatus != XDPTX_PHY_STATUS_ALL_LANES_READY_MASK);
while (PhyStatus != Mask);
return XST_SUCCESS;
}