![]() Write to CRL_APB registers for clock control and enable 1G speed. Move clock configuration to a separate function. Update payload to jumbo size. Signed-off-by: Harini Katakam <harinik@xilinx.com> Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> |
||
---|---|---|
.. | ||
data | ||
examples | ||
src |