3f6f63b07e
This patch unifies standalone for both Zynq and ZynqMP platforms. Also follows misrac guidelines. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
114 lines
4.7 KiB
C
114 lines
4.7 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file smc.h
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 1.00a sdm 11/03/09 Initial release.
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* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
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* as smc.c is removed
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* </pre>
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*
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* @note None.
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*
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******************************************************************************/
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#ifndef SMC_H /* prevent circular inclusions */
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#define SMC_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xparameters.h"
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#include "xil_io.h"
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/***************** Macros (Inline Functions) Definitions *********************/
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/**************************** Type Definitions *******************************/
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/************************** Constant Definitions *****************************/
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/* Memory controller configuration register offset */
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#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
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#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
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#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
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#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
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#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
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#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
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#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
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#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
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#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
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/* Chip select configuration register offset */
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#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
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#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
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#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
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#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
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#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
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#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
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#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
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#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
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/* User configuration register offset */
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#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
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#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
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/* Integration test register offset */
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#define XSMCPSS_IT_OFFSET 0xE00U
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/* ID configuration register offset */
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#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
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#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
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#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
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#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
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#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
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#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
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#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
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#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* SMC_H */
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