141 lines
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141 lines
9.3 KiB
HTML
Executable file
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<title>llfifo: Main Page</title>
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<div id="projectname">llfifo
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<div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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<li class="current"><a href="index.html"><span>Overview</span></a></li>
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<li><a href="annotated.html"><span>Data Structures</span></a></li>
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<li><a href="globals.html"><span>APIs</span></a></li>
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<li><a href="files.html"><span>File List</span></a></li>
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<div class="title">llfifo Documentation</div> </div>
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<div class="contents">
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<div class="textblock"><p>The Xilinx Dual Channel Fifo driver component. This driver supports the Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.</p>
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<p>For a full description of the bridge features, please see the HW spec. This driver supports the following features:</p><ul>
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<li>Memory mapped access to host interface registers</li>
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<li>API for polled frame transfers</li>
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<li>API for interrupt driven frame transfers</li>
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<li>Virtual memory support</li>
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<li>Full duplex operation</li>
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</ul>
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<h2>Driver Description</h2>
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<p>This driver enables higher layer software to access the XPS_llFifo core using any alignment in the data buffers.</p>
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<p>This driver supports send and receive channels in the same instance structure in the same fashion as the hardware core.</p>
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<h2>Initialization</h2>
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<p>An instance of this driver is initialized using a call to Initialize().</p>
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<h2>Usage</h2>
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<p>It is fairly simple to use the API provided by this FIFO driver. The only somewhat tricky part is that the calling code must correctly call a couple routines in the right sequence for receive and transmit.</p>
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<p>This sequence is described here. Check the routine functional descriptions for information on how to use a specific API routine.</p>
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<h3>Receive</h3>
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<p>A frame is received by using the following sequence:<br />
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1) call <a class="el" href="group__llfifo__v5__0.html#ga12da547aa1c9a85e2b0b151f438ff9d5" title="XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to be read from the rece...">XLlFifo_RxOccupancy()</a> to check the occupancy count<br />
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2) call <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e" title="XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the r...">XLlFifo_RxGetLen()</a> to get the length of the next incoming frame<br />
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3) call <a class="el" href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03" title="XLlFifo_Read reads Bytes bytes from the receive channel of the FIFO referenced by InstancePtr to the ...">XLlFifo_Read()</a> one or more times to read the number of bytes reported by <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e" title="XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the r...">XLlFifo_RxGetLen()</a>.<br />
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</p>
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<p>For example: </p><pre>
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while (<a class="el" href="group__llfifo__v5__0.html#ga12da547aa1c9a85e2b0b151f438ff9d5" title="XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to be read from the rece...">XLlFifo_RxOccupancy(&RxInstance)</a>) {
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frame_len = <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e" title="XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the r...">XLlFifo_RxGetLen(&RxInstance)</a>;
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while (frame_len) {
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unsigned bytes = min(sizeof(buffer), frame_len);
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<a class="el" href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03" title="XLlFifo_Read reads Bytes bytes from the receive channel of the FIFO referenced by InstancePtr to the ...">XLlFifo_Read(&RxInstance, buffer, bytes)</a>;
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// ********
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// do something with buffer here
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// ********
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frame_len -= bytes;
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}
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}
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</pre><p>This FIFO hardware core does <b>not</b> support a sequence where the calling code calls RxGetLen() twice in a row and then receive the data for two frames. Each frame must be read in by calling RxGetLen() just prior to reading the data.</p>
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<h3>Transmit</h3>
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<p>A frame is transmittted by using the following sequence:<br />
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1) call <a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295" title="XLlFifo_Write writes Bytes bytes of the block of memory, referenced by BufPtr, to the transmit channe...">XLlFifo_Write()</a> one or more times to write all the of bytes in the next frame.<br />
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2) call <a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7" title="XLlFifo_TxSetLen begins a hardware transfer of Bytes bytes out of the transmit channel of the FIFO sp...">XLlFifo_TxSetLen()</a> to begin the transmission of frame just written.<br />
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</p>
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<p>For example: </p><pre>
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frame_left = frame_len;
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while (frame_left) {
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unsigned bytes = min(sizeof(buffer), frame_left);
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<a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295" title="XLlFifo_Write writes Bytes bytes of the block of memory, referenced by BufPtr, to the transmit channe...">XLlFifo_Write(&TxInstance, buffer, bytes)</a>;
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// ********
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// do something here to refill buffer
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// ********
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frame_left -= bytes;
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}
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<a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7" title="XLlFifo_TxSetLen begins a hardware transfer of Bytes bytes out of the transmit channel of the FIFO sp...">XLlFifo_TxSetLen(&RxInstance, frame_len)</a>;
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</pre><p>This FIFO hardware core does <b>not</b> support a sequence where the calling code writes the data for two frames and then calls TxSetLen() twice in a row. Each frame must be written by writting the data for one frame and then calling TxSetLen().</p>
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<h2>Interrupts</h2>
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<p>This driver does not handle interrupts from the FIFO hardware. The software layer above may make use of the interrupts by setting up its own handlers for the interrupts.</p>
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<pre>
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MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
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----- ---- -------- -------------------------------------------------------
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1.00a jvb 10/12/06 First release
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1.01a sdm 08/22/08 Removed support for static interrupt handlers from the
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MDD file
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1.02a jz 12/04/09 Hal phase 1 support
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2.01a asa 09/17/10 Added code for resetting Local Link/AXI Streaming
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interface for CR574868
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2.02a asa 12/27/11 Changed the function XStrm_Read in xtreamer.c to reset
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HeadIndex to zero when all bytes have been read.
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Changed the macro XStrm_IsRxInternalEmpty in file
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xtreamer.h to use FrmByteCnt instead of HeadIndex.
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When FrmByteCnt is zero, this means all internal buffers
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in streamer are empty. Earlier implementation using
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HeadIndex was not very clear and could give improper
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results for some cases.
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Changed the macro XLlFifo_IsRxEmpty in file <a class="el" href="xllfifo_8h.html">xllfifo.h</a>
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These changes are done to fix the CR 604650.
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2.03a asa 14/08/12 Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
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defines for the new registers, and XLLF_INT_TFPF_MASK,
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XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
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XLLF_INT_RFPE_MASK for the new version of the
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AXI4-Stream FIFO core (v2.01a and later)</pre><pre> 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are
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In <a class="el" href="xllfifo_8c.html">Xllfifo.c</a> file XLlFifo_RxGetWord,XLlFifo_TxPutword.
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In <a class="el" href="xllfifo_8h.html">XLlfifo.h</a> file updated XLlfifo structure for
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Axi4BaseAddress and for Datainterface type provided
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polling and interrupt examples. XLlfifo_IsRxDone Macro
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Is added in the <a class="el" href="xllfifo_8h.html">XLlfifo.h</a> file for polledmode exmaple.
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Added Static initialzation for the driver.
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XLlFifo_Initialize is still used to make the driver
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backward compatible.
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4.0 adk 19/12/13 Updated as per the New Tcl API's
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5.0 adk 15/05/15 Updated the register offsets in the AXI4 data path
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as per latest IP version(v4.1)(CR:860254).</pre><pre> </pre> </div></div><!-- contents -->
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<li class="footer">Copyright © 2015 Xilinx Inc. All rights reserved.</li>
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