Rohit Consul 759573e90f v_hscaler: Bug Fix in phase calculation logic ... 4 Samples/Clock phase calculation logic works on 64bit entities. However a 32bit variable was used that caused wrong phase information to be generated. Updated relevant variables to 64b Signed-off-by: Rohit Consul <rohit.consul@xilinx.com> Reviewed-by: Andrei Simion <andreis@xilinx.com>		2015-08-04 14:11:38 +05:30
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data	v_hscaler: Added multiple pixel per clock support	2015-08-04 14:10:22 +05:30
src	v_hscaler: Bug Fix in phase calculation logic	2015-08-04 14:11:38 +05:30