-There was a bug in pmu-fw/pm binding through IPIs, because of
which in case of multiple IPI interrupts generated simultaneously
only first interrupt was handled, other interrupts were lost
-The bug existed because PM handles one request in each
XPfw_PmIpiHandler invocation, and pmu-fw clears all bitfields
in ISR register after PM handles request. Therefore, if multiple
bits were set in ISR register (simultaneous IPI interrupts), only
first one was handled and other bits were just cleared
-XPfw_PmIpiHandler now returns status and through an argument
pointer an IPI mask of master whose request has been handled
-In xpfw_user_startup.c/PmIpiHandler, return of XPfw_PmIpiHandler
is checked. If PM successfully handled IPI, only the bitfield of
master whose request is handled is set (only that IPI interrupt
is cleared). If something went wrong in PmIpiHandler/IPI0 case,
we clear all bits set in ISR register, to avoid system hanging on
this interrupt handler
-In pm_master, a check whether the master owns given mask was
performed by using '==' instead '&'. Therefore, when 2 masters
generated interrupt at the same time, PM function that checks
whether the IPI is PM related returned that the ISR value does
not match any master. This bug is fixed
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
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