embeddedsw/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest
Shakti Bhatnagar 9a04f2c373 nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp.
Added driver to supports Arasan NAND controller present in
Zynq Ultrascale Mp.

Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
2014-12-09 20:32:14 +05:30
..
ct.h nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
ct_standalone.c nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
intg.c nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
intg.h nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
intg_ecc_test.c nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
intg_erase_read.c nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
intg_flash_rw.c nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
intg_partialpage_rw.c nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
intg_random_rw.c nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
intg_sparebytes_rw.c nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
README.txt nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30
xil_testlib.h nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp. 2014-12-09 20:32:14 +05:30

NandPs8 Integration test

- On A53 processors use the linker script for DDR region to run the integration test
  With OCM linker script which is the default linker script, the integration test may hang.
  In order to run on OCM, you can use Xil_DCacheDisable() in the main and run the integration test.

- On R5 processors, you may get compilation error for bsp stating "undefined reference to `end'"
  Add end = .;  at the end of the linker script to remove this error

  } > ps8_ocm_ram_0_S_AXI_BASEADDR

  _end = .;
  end = .;
}