c46210930c
This patch converts the three line comments to single line Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
317 lines
13 KiB
C
317 lines
13 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xnandpsu_onfi.h
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* @addtogroup nandpsu_v1_0
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* @{
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*
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* This file defines all the ONFI 3.1 specific commands and values.
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*
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* @note None
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- ---------- -----------------------------------------------
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* 1.0 nm 05/06/2014 First release
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* </pre>
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*
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******************************************************************************/
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#ifndef XNANDPSU_ONFI_H /* prevent circular inclusions */
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#define XNANDPSU_ONFI_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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/************************** Constant Definitions *****************************/
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/* Standard ONFI 3.1 Commands */
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/* ONFI 3.1 Mandatory Commands */
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#define ONFI_CMD_RD1 0x00U /**< Read (1st cycle) */
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#define ONFI_CMD_RD2 0x30U /**< Read (2nd cycle) */
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#define ONFI_CMD_CHNG_RD_COL1 0x05U /**< Change Read Column
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(1st cycle) */
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#define ONFI_CMD_CHNG_RD_COL2 0xE0U /**< Change Read Column
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(2nd cycle) */
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#define ONFI_CMD_BLK_ERASE1 0x60U /**< Block Erase (1st cycle) */
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#define ONFI_CMD_BLK_ERASE2 0xD0U /**< Block Erase (2nd cycle) */
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#define ONFI_CMD_RD_STS 0x70U /**< Read Status */
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#define ONFI_CMD_PG_PROG1 0x80U /**< Page Program(1st cycle) */
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#define ONFI_CMD_PG_PROG2 0x10U /**< Page Program(2nd cycle) */
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#define ONFI_CMD_CHNG_WR_COL 0x85U /**< Change Write Column */
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#define ONFI_CMD_RD_ID 0x90U /**< Read ID */
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#define ONFI_CMD_RD_PRM_PG 0xECU /**< Read Parameter Page */
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#define ONFI_CMD_RST 0xFFU /**< Reset */
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/* ONFI 3.1 Optional Commands */
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#define ONFI_CMD_MUL_RD1 0x00U /**< Multiplane Read
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(1st cycle) */
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#define ONFI_CMD_MUL_RD2 0x32U /**< Multiplane Read
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(2nd cycle) */
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#define ONFI_CMD_CPBK_RD1 0x00U /**< Copyback Read
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(1st cycle) */
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#define ONFI_CMD_CPBK_RD2 0x35U /**< Copyback Read
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(2nd cycle) */
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#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U /**< Change Read Column
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Enhanced (1st cycle) */
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#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U /**< Change Read Column
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Enhanced (2nd cycle) */
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#define ONFI_CMD_RD_CACHE_RND1 0x00U /**< Read Cache Random
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(1st cycle) */
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#define ONFI_CMD_RD_CACHE_RND2 0x31U /**< Read Cache Random
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(2nd cycle) */
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#define ONFI_CMD_RD_CACHE_SEQ 0x31U /**< Read Cache Sequential */
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#define ONFI_CMD_RD_CACHE_END 0x3FU /**< Read Cache End */
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#define ONFI_CMD_MUL_BLK_ERASE1 0x60U /**< Multiplane Block Erase
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(1st cycle) */
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#define ONFI_CMD_MUL_BLK_ERASE2 0xD1U /**< Multiplane Block Erase
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(2nd cycle) */
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#define ONFI_CMD_RD_STS_ENHCD 0x78U /**< Read Status Enhanced */
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#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U /**< Block Erase Interleaved
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(2nd cycle) */
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#define ONFI_CMD_MUL_PG_PROG1 0x80U /**< Multiplane Page Program
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(1st cycle) */
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#define ONFI_CMD_MUL_PG_PROG2 0x11U /**< Multiplane Page Program
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(2nd cycle) */
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#define ONFI_CMD_PG_CACHE_PROG1 0x80U /**< Page Cache Program
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(1st cycle) */
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#define ONFI_CMD_PG_CACHE_PROG2 0x15U /**< Page Cache Program
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(2nd cycle) */
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#define ONFI_CMD_CPBK_PROG1 0x85U /**< Copyback Program
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(1st cycle) */
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#define ONFI_CMD_CPBK_PROG2 0x10U /**< Copyback Program
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(2nd cycle) */
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#define ONFI_CMD_MUL_CPBK_PROG1 0x85U /**< Multiplane Copyback
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Program (1st cycle) */
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#define ONFI_CMD_MUL_CPBK_PROG2 0x10U /**< Multiplane Copyback
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Program (2nd cycle) */
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#define ONFI_CMD_SMALL_DATA_MV1 0x85U /**< Small Data Move
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(1st cycle) */
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#define ONFI_CMD_SMALL_DATA_MV2 0x10U /**< Small Data Move
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(2nd cycle) */
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#define ONFI_CMD_CHNG_ROW_ADDR 0x85U /**< Change Row Address */
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#define ONFI_CMD_VOL_SEL 0xE1U /**< Volume Select */
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#define ONFI_CMD_ODT_CONF 0xE2U /**< ODT Configure */
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#define ONFI_CMD_RD_UNIQID 0xEDU /**< Read Unique ID */
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#define ONFI_CMD_GET_FEATURES 0xEEU /**< Get Features */
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#define ONFI_CMD_SET_FEATURES 0xEFU /**< Set Features */
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#define ONFI_CMD_LUN_GET_FEATURES 0xD4U /**< LUN Get Features */
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#define ONFI_CMD_LUN_SET_FEATURES 0xD5U /**< LUN Set Features */
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#define ONFI_CMD_RST_LUN 0xFAU /**< Reset LUN */
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#define ONFI_CMD_SYN_RST 0xFCU /**< Synchronous Reset */
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/* ONFI Status Register bit offsets */
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#define ONFI_STS_FAIL 0x01U /**< FAIL */
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#define ONFI_STS_FAILC 0x02U /**< FAILC */
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#define ONFI_STS_CSP 0x08U /**< CSP */
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#define ONFI_STS_VSP 0x10U /**< VSP */
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#define ONFI_STS_ARDY 0x20U /**< ARDY */
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#define ONFI_STS_RDY 0x40U /**< RDY */
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#define ONFI_STS_WP 0x80U /**< WP_n */
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/* ONFI constants */
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#define ONFI_CRC_LEN 254U /**< ONFI CRC Buf Length */
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#define ONFI_PRM_PG_LEN 256U /**< Parameter Page Length */
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#define ONFI_MND_PRM_PGS 3U /**< Number of mandatory
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parameter pages */
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#define ONFI_SIG_LEN 4U /**< Signature Length */
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#define ONFI_CMD_INVALID 0x00U /**< Invalid Command */
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#define ONFI_READ_ID_LEN 4U /**< ONFI ID length */
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#define ONFI_READ_ID_ADDR 0x20U /**< ONFI Read ID Address */
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#define ONFI_READ_ID_ADDR_CYCLES 1U /**< ONFI Read ID Address
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cycles */
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#define ONFI_PRM_PG_ADDR_CYCLES 1U /**< ONFI Read Parameter page
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address cycles */
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/**
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* This enum defines the ONFI 3.1 commands.
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*/
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enum OnfiCommandList {
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READ=0, /**< Read */
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MULTIPLANE_READ, /**< Multiplane Read */
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COPYBACK_READ, /**< Copyback Read */
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CHANGE_READ_COLUMN, /**< Change Read Column */
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CHANGE_READ_COLUMN_ENHANCED, /**< Change Read Column Enhanced */
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READ_CACHE_RANDOM, /**< Read Cache Random */
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READ_CACHE_SEQUENTIAL, /**< Read Cache Sequential */
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READ_CACHE_END, /**< Read Cache End */
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BLOCK_ERASE, /**< Block Erase */
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MULTIPLANE_BLOCK_ERASE, /**< Multiplane Block Erase */
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READ_STATUS, /**< Read Status */
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READ_STATUS_ENHANCED, /**< Read Status Enhanced */
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PAGE_PROGRAM, /**< Page Program */
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MULTIPLANE_PAGE_PROGRAM, /**< Multiplane Page Program */
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PAGE_CACHE_PROGRAM, /**< Page Cache Program */
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COPYBACK_PROGRAM, /**< Copyback Program */
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MULTIPLANE_COPYBACK_PROGRAM, /**< Multiplance Copyback Program */
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SMALL_DATA_MOVE, /**< Small Data Move */
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CHANGE_WRITE_COLUMN, /**< Change Write Column */
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CHANGE_ROW_ADDR, /**< Change Row Address */
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READ_ID, /**< Read ID */
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VOLUME_SELECT, /**< Volume Select */
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ODT_CONFIGURE, /**< ODT Configure */
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READ_PARAM_PAGE, /**< Read Parameter Page */
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READ_UNIQUE_ID, /**< Read Unique ID */
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GET_FEATURES, /**< Get Features */
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SET_FEATURES, /**< Set Features */
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LUN_GET_FEATURES, /**< LUN Get Features */
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LUN_SET_FEATURES, /**< LUN Set Features */
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RESET_LUN, /**< Reset LUN */
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SYN_RESET, /**< Synchronous Reset */
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RESET, /**< Reset */
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MAX_CMDS /**< Dummy Command */
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};
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/**************************** Type Definitions *******************************/
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/* Parameter page structure of ONFI 3.1 specification. */
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typedef struct {
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/* Revision information and features block */
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u8 Signature[4]; /**< Parameter page signature */
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u16 Revision; /**< Revision Number */
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u16 Features; /**< Features supported */
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u16 OptionalCmds; /**< Optional commands supported */
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u8 JedecJtgPrmAdvCmd; /**< ONFI JEDEC JTG primary advanced
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command support */
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u8 Reserved0; /**< Reserved (11) */
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u16 ExtParamPageLen; /**< Extended Parameter Page Length */
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u8 NumOfParamPages; /**< Number of Parameter Pages */
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u8 Reserved1[17]; /**< Reserved (15-31) */
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/* Manufacturer information block */
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u8 DeviceManufacturer[12]; /**< Device manufacturer */
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u8 DeviceModel[20]; /**< Device model */
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u8 JedecManufacturerId; /**< JEDEC Manufacturer ID */
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u8 DateCode[2]; /**< Date code */
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u8 Reserved2[13]; /**< Reserved (67-79) */
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/* Memory organization block */
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u32 BytesPerPage; /**< Number of data bytes per page */
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u16 SpareBytesPerPage; /**< Number of spare bytes per page */
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u32 BytesPerPartialPage; /**< Number of data bytes per
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partial page */
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u16 SpareBytesPerPartialPage; /**< Number of spare bytes per
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partial page */
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u32 PagesPerBlock; /**< Number of pages per block */
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u32 BlocksPerLun; /**< Number of blocks per LUN */
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u8 NumLuns; /**< Number of LUN's */
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u8 AddrCycles; /**< Number of address cycles */
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u8 BitsPerCell; /**< Number of bits per cell */
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u16 MaxBadBlocksPerLun; /**< Bad blocks maximum per LUN */
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u16 BlockEndurance; /**< Block endurance */
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u8 GuaranteedValidBlock; /**< Guaranteed valid blocks at
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beginning of target */
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u16 BlockEnduranceGVB; /**< Block endurance for guaranteed
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valid block */
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u8 ProgramsPerPage; /**< Number of programs per page */
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u8 PartialProgAttr; /**< Partial programming attributes */
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u8 EccBits; /**< Number of bits ECC
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correctability */
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u8 PlaneAddrBits; /**< Number of plane address bits */
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u8 PlaneOperationAttr; /**< Multi-plane operation
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attributes */
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u8 EzNandSupport; /**< EZ NAND support */
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u8 Reserved3[12]; /**< Reserved (116 - 127) */
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/* Electrical parameters block */
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u8 IOPinCapacitance; /**< I/O pin capacitance, maximum */
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u16 SDRTimingMode; /**< SDR Timing mode support */
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u16 SDRPagecacheTimingMode; /**< SDR Program cache timing mode */
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u16 TProg; /**< Maximum page program time */
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u16 TBers; /**< Maximum block erase time */
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u16 TR; /**< Maximum page read time */
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u16 TCcs; /**< Maximum change column setup
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time */
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u8 NVDDRTimingMode; /**< NVDDR timing mode support */
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u8 NVDDR2TimingMode; /**< NVDDR2 timing mode support */
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u8 SynFeatures; /**< NVDDR/NVDDR2 features */
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u16 ClkInputPinCap; /**< CLK input pin capacitance */
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u16 IOPinCap; /**< I/O pin capacitance */
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u16 InputPinCap; /**< Input pin capacitance typical */
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u8 InputPinCapMax; /**< Input pin capacitance maximum */
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u8 DrvStrength; /**< Driver strength support */
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u16 TMr; /**< Maximum multi-plane read time */
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u16 TAdl; /**< Program page register clear
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enhancement value */
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u16 TEr; /**< Typical page read time for
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EZ NAND */
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u8 NVDDR2Features; /**< NVDDR2 Features */
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u8 NVDDR2WarmupCycles; /**< NVDDR2 Warmup Cycles */
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u8 Reserved4[4]; /**< Reserved (160 - 163) */
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/* Vendor block */
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u16 VendorRevisionNum; /**< Vendor specific revision number */
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u8 VendorSpecific[88]; /**< Vendor specific */
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u16 Crc; /**< Integrity CRC */
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}__attribute__((packed))OnfiParamPage;
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/* ONFI extended parameter page structure. */
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typedef struct {
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u16 Crc;
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u8 Sig[4];
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u8 Reserved1[10];
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u8 Section0Type;
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u8 Section0Len;
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u8 Section1Type;
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u8 Section1Len;
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u8 ResSection[12];
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u8 SectionData[256];
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}__attribute__((packed))OnfiExtPrmPage;
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/* Driver extended parameter page information. */
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typedef struct {
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u8 NumEccBits;
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u8 CodeWordSize;
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u16 MaxBadBlocks;
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u16 BlockEndurance;
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u16 Reserved;
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}__attribute__((packed))OnfiExtEccBlock;
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typedef struct {
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u8 Command1; /**< Command Cycle 1 */
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u8 Command2; /**< Command Cycle 2 */
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} OnfiCmdFormat;
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extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
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/************************** Function Prototypes ******************************/
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u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
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#ifdef __cplusplus
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}
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#endif
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#endif /* XNANDPSU_ONFI_H end of protection macro */
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/** @} */
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