embeddedsw/XilinxProcessorIPLib/drivers/nandpsu/doc/html/api/index.html
Nava kishore Manne d18411f597 Drivers: Doxygen changes for 2015.4
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2015-12-01 11:51:28 +05:30

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<div class="title">nandpsu Documentation</div> </div>
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<div class="textblock"><p>This file implements a driver to support Arasan NAND controller present in Zynq Ultrascale Mp.<b>Driver Initialization</b></p>
<p>The function call <a class="el" href="group__nandpsu__v1__0.html#ga8268e05a9d1a0339dc2ec672d7dd8c79" title="This function initializes a specific XNandPsu instance. ">XNandPsu_CfgInitialize()</a> should be called by the application before any other function in the driver. The initialization function takes device specific data (like device id, instance id, and base address) and initializes the <a class="el" href="struct_x_nand_psu.html" title="The XNandPsu structure contains the driver instance data. ">XNandPsu</a> instance with the device specific data.</p>
<p><b>Device Geometry</b></p>
<p>NAND flash device is memory device and it is segmented into areas called Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device can have multiple LUN. LUN is sequential raw of multiple blocks of the same size. A block is the smallest erasable unit of data within the Flash array of a LUN. The size of each block is based on a power of 2. There is no restriction on the number of blocks within the LUN. A block contains a number of pages. A page is the smallest addressable unit for read and program operations. The arrangement of LUN, blocks, and pages is referred to by this module as the part's geometry.</p>
<p>The cells within the part can be programmed from a logic 1 to a logic 0 and not the other way around. To change a cell back to a logic 1, the entire block containing that cell must be erased. When a block is erased all bytes contain the value 0xFF. The number of times a block can be erased is finite. Eventually the block will wear out and will no longer be capable of erasure. As of this writing, the typical flash block can be erased 100,000 or more times.</p>
<p>The jobs done by this driver typically are:</p><ul>
<li>8-bit operational mode</li>
<li>Read, Write, and Erase operation</li>
</ul>
<p><b>Write Operation</b></p>
<p>The write call can be used to write a minimum of one byte and a maximum entire flash. If the address offset specified to write is out of flash or if the number of bytes specified from the offset exceed flash boundaries an error is reported back to the user. The write is blocking in nature in that the control is returned back to user only after the write operation is completed successfully or an error is reported.</p>
<p><b>Read Operation</b></p>
<p>The read call can be used to read a minimum of one byte and maximum of entire flash. If the address offset specified to read is out of flash or if the number of bytes specified from the offset exceed flash boundaries an error is reported back to the user. The read is blocking in nature in that the control is returned back to user only after the read operation is completed successfully or an error is reported.</p>
<p><b>Erase Operation</b></p>
<p>The erase operations are provided to erase a Block in the Flash memory. The erase call is blocking in nature in that the control is returned back to user only after the erase operation is completed successfully or an error is reported.</p>
<dl class="section note"><dt>Note</dt><dd>Driver has been renamed to nandpsu after change in naming convention.</dd></dl>
<p>This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads, mutual exclusion, virtual memory, cache control, or HW write protection management must be satisfied by the layer above this driver.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver Who Date Changes
----- ---- ---------- -----------------------------------------------
1.0 nm 05/06/2014 First release
2.0 sb 01/12/2015 Removed Null checks for Buffer passed
as parameter to Read API's</p><ul>
<li><a class="el" href="group__nandpsu__v1__0.html#gad7e291db556ad9d33fbd06aa6ab79cb6" title="This function reads from the flash. ">XNandPsu_Read()</a></li>
<li>XNandPsu_ReadPage
Modified</li>
<li><a class="el" href="group__nandpsu__v1__0.html#ga785eaf418c8f7e7c3fb6098ba327b720" title="This function sends ONFI Set Feature command to flash. ">XNandPsu_SetFeature()</a></li>
<li><a class="el" href="group__nandpsu__v1__0.html#gaa6725c5aa761078a438094bad802045e" title="This function sends ONFI Get Feature command to flash. ">XNandPsu_GetFeature()</a>
and made them public.
Removed Failure Return for BCF Error check in
XNandPsu_ReadPage() and added BCH_Error counter
in the instance pointer structure.
Added XNandPsu_Prepare_Cmd API
Replaced</li>
<li>XNandPsu_IntrStsEnable</li>
<li>XNandPsu_IntrStsClear</li>
<li>XNandPsu_IntrClear</li>
<li>XNandPsu_SetProgramReg
with XNandPsu_WriteReg call
Modified <a class="el" href="xnandpsu_8c.html">xnandpsu.c</a> file API's with above changes.
Corrected the program command for Set Feature API.
Modified</li>
<li>XNandPsu_OnfiReadStatus</li>
<li>XNandPsu_GetFeature</li>
<li>XNandPsu_SetFeature
to add support for DDR mode.
Changed Convention for SLC/MLC
SLC --&gt; HAMMING
MLC --&gt; BCH
SlcMlc --&gt; IsBCH
Added support for writing BBT signature and version
in page section by enabling XNANDPSU_BBT_NO_OOB.
Removed extra DMA mode initialization from
the XNandPsu_CfgInitialize API.
Modified</li>
<li>XNandPsu_SetEccAddrSize
ECC address now is calculated based upon the
size of spare area
Modified Block Erase API, removed clearing of
packet register before erase.
Clearing Data Interface Register before
XNandPsu_OnfiReset call.
Modified XNandPsu_ChangeTimingMode API supporting
SDR and NVDDR interface for timing modes 0 to 5.
Modified Bbt Signature and Version Offset value for
Oob and No-Oob region.
1.0 kpc 17/06/2015 Increased the timeout for complete event to avoid
timeout errors for erase operation on slower devices.
</li>
</ul>
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