103 lines
6.9 KiB
HTML
Executable file
103 lines
6.9 KiB
HTML
Executable file
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<title>tft: Main Page</title>
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<div id="projectname">tft
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<div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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<ul class="tablist">
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<li class="current"><a href="index.html"><span>Overview</span></a></li>
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<li><a href="annotated.html"><span>Data Structures</span></a></li>
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<li><a href="globals.html"><span>APIs</span></a></li>
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<li><a href="files.html"><span>File List</span></a></li>
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<div class="title">tft Documentation</div> </div>
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<div class="contents">
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<div class="textblock"><p>This header file contains the definitions and declarations for the high level driver to access the Xilinx TFT Controller Device. The device has the capability of displaying data onto a 640*480 VGA TFT screen. It can take up to 256K colors. There is no interrupt mode.</p>
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<p>The functions XTft_Setpixel and XTft_Getpixel are provided in the driver to write to and read from the individual pixels, the color values.</p>
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<p>These are generally stored in the assigned 2MB Video Memory which is configurable.</p>
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<p>Video Memory stores each pixel value in 32bits. Out of this 2MB memory which can hold 1024 pixels per line and 512 lines per frame data, only 640 pixels per line and 480 lines per frame are used.</p>
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<p>Each base color Red, Green, Blue is encoded using 6 bits which sums up to 18bits which is stored in the Dual port BRAM.</p>
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<p><b>Initialization & Configuration</b></p>
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<p>The <a class="el" href="struct_x_tft___config.html" title="This structure holds the Device base address, video memory base address and Unique identifier of the ...">XTft_Config</a> structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.</p>
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<p>To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized as follows:</p>
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<ul>
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<li>XTft_CfgInitialize(InstancePtr, CfgPtr, BaseAddress) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure.</li>
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</ul>
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<p><b>Interrupts</b></p>
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<p>The TFT device supports a single interrupt which is generated for a Vsync pulse.</p>
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<p>This driver does not provide a Interrupt Service Routine (ISR) for the device. It is the responsibility of the application to provide one if needed.</p>
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<p><b>RTOS Independence</b></p>
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<p>This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</p>
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<pre>
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MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
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----- ---- -------- -----------------------------------------------
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1.00a sg 03/24/08 First release
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2.00a ktn 07/06/09 Added <a class="el" href="group__tft__v5__0.html#ga3241465696077377ea4000f4caca21a7" title="This function enables the Vsync Interrupt in the Interrupt Enable and Status Register. ">XTft_IntrEnable()</a>, <a class="el" href="group__tft__v5__0.html#ga1bc1f7d9c152c6e661cd125f4c190dd8" title="This function disables the Vsync Interrupt in the Interrupt Enable and Status Register. ">XTft_IntrDisable()</a>and,
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<a class="el" href="group__tft__v5__0.html#gacc8325682d029d3618ff0a7d6ee265dc" title="This function gets the Vsync(Video address latch) status from the Interrupt Enable and Status Registe...">XTft_GetVsyncStatus()</a> functions to access newly added
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Interrupt Enable and Status Register.
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3.00a ktn 10/22/09 Updated driver to use the HAL APIs/macros.
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Removed the macros XTft_mSetPixel and XTft_mGetPixel.
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3.00a bss 01/16/12 Updated driver to remove warnings from asserts.
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3.01a sg 05/30/12 Corrected the brace error introduced in
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XTft_GetPixel while changing it from macro to
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function for CR 647750.
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3.02a bss 11/30/12 CR 690338 - Corrected the brace error introduced in
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XTft_GetPixel for CR 647750.
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4.00a bss 01/25/13 Added support for AXI TFT controller, this driver
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can only be used for AXI TFT controller
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XTft_WriteReg and XTft_ReadReg functions are updated
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Removed all functionality associated with DCR access
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PlbAccess and DcrBaseAddr are removed from the
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<a class="el" href="struct_x_tft___config.html" title="This structure holds the Device base address, video memory base address and Unique identifier of the ...">XTft_Config</a> config structure
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4.01a bss 11/01/13 Modified driver tcl to retrieve C_BASEADDR/C_HIGHADDR
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CR#757359.
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5.0 adk 19/12/13 Updated as per the New Tcl API's
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6.0 sd 19/08/15 Updated the BaseAddress and VideoMemBaseAddr
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variables in <a class="el" href="struct_x_tft___config.html" title="This structure holds the Device base address, video memory base address and Unique identifier of the ...">XTft_Config</a> to be UINTPTR to support
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64 bit addresses. Added AddrWidth to the
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<a class="el" href="struct_x_tft___config.html" title="This structure holds the Device base address, video memory base address and Unique identifier of the ...">XTft_Config</a> structure which reflects the value of
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C_M_AXI_ADDR_WIDTH.
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Updated to tcl add the C_M_AXI_ADDR_WIDTH parameter.
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Added XTFT_AR_LSB_OFFSET and XTFT_AR_MSB_OFFSET
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definitions to the <a class="el" href="xtft__hw_8h.html">xtft_hw.h</a> file, these offsets
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are valid only when the Address Width is greater
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than 32 bits.
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*</pre> </div></div><!-- contents -->
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<li class="footer">Copyright © 2015 Xilinx Inc. All rights reserved.</li>
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