embeddedsw/XilinxProcessorIPLib/drivers/v_hscaler/src
Rohit Consul 759573e90f v_hscaler: Bug Fix in phase calculation logic
4 Samples/Clock phase calculation logic works on 64bit entities.
However a 32bit variable was used that caused wrong phase
information to be generated. Updated relevant variables to 64b

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:11:38 +05:30
..
Makefile v_hscaler: Added new driver 2015-06-09 16:25:53 +05:30
xv_hscaler.c v_hscaler: Updated driver to align with hip flow 2015-07-23 11:00:40 +05:30
xv_hscaler.h v_hscaler: Updated driver to align with hip flow 2015-07-23 11:00:40 +05:30
xv_hscaler_coeff.c v_hscaler: Added multiple pixel per clock support 2015-08-04 14:10:22 +05:30
xv_hscaler_g.c v_hscaler: Updated driver to align with hip flow 2015-07-23 11:00:40 +05:30
xv_hscaler_hw.h v_hscaler: Added new driver 2015-06-09 16:25:53 +05:30
xv_hscaler_l2.c v_hscaler: Bug Fix in phase calculation logic 2015-08-04 14:11:38 +05:30
xv_hscaler_l2.h v_hscaler: Added multiple pixel per clock support 2015-08-04 14:10:22 +05:30
xv_hscaler_linux.c v_hscaler: Updated driver to align with hip flow 2015-07-23 11:00:40 +05:30
xv_hscaler_sinit.c v_hscaler: Updated driver to align with hip flow 2015-07-23 11:00:40 +05:30