206 lines
4 KiB
C
206 lines
4 KiB
C
/*
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* Copyright 2013 Steffen Vogel, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*/
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/**
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* @author Steffen Vogel
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* @file arch/x86/kernel/pmc.c
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* @brief Simple interface to IA32 Performance Monitor Counters
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*
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* This implementation is in parts specific for Intel Core 2 Duo Processors!
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* General purpose PMCS => pmc_gp_*()
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* Fixed function PMCs => pmc_ff_*()
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*/
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#include <errno.h>
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#include <asm/pmc.h>
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#include <asm/processor.h>
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static struct pmc_caps caps = { 0 };
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struct pmc_caps* pmc_init()
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{
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if (!caps.version) {
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uint32_t a, b, c, d;
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cpuid(0x0A, &a, &b, &c, &d);
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caps.version = (a >> 0) & 0xff;
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caps.gp_count = (a >> 8) & 0xff;
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caps.gp_width = (a >> 16) & 0xff;
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caps.ff_count = (d >> 0) & 0x1f;
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caps.ff_width = (d >> 5) & 0xff;
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caps.arch_events = (b >> 0) & 0x3f;
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// check if IA32_PERF_CAPABILITIES MSR is available
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if (caps.version >= 2) {
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cpuid(0x01, &a, &b, &c, &d);
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if (c & (1 << 15 /* PDCM */))
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caps.msr = rdmsr(IA32_PERF_CAPABILITIES);
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}
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}
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return ∩︀
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}
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int pmc_gp_config(uint8_t i, uint16_t event, uint32_t flags, uint8_t umask, uint8_t cmask)
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{
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if (BUILTIN_EXPECT(i > caps.gp_count, 0))
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return -EINVAL;
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uint64_t evtsel = flags | event;
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evtsel |= (cmask << PMC_EVTSEL_CMASK) | (umask << PMC_EVTSEL_UMASK);
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wrmsr(IA32_PERFEVTSEL(i), evtsel);
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wrmsr(IA32_PMC(i), 0); // reset counter
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return 0;
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}
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int pmc_ff_config(uint8_t i, uint8_t flags)
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{
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if (BUILTIN_EXPECT(i > caps.ff_count, 0))
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return -EINVAL;
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uint64_t ctrl = rdmsr(MSR_PERF_FIXED_CTR_CTRL);
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ctrl &= ~(0x0f << i*4); // clear flags
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ctrl |= (flags & 0xf) << i*4;
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wrmsr(MSR_PERF_FIXED_CTR_CTRL, ctrl);
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return 0;
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}
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inline int pmc_gp_start(uint8_t i)
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{
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if (BUILTIN_EXPECT(i > caps.gp_count, 0))
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return -EINVAL;
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wrmsr(IA32_PERFEVTSEL(i), rdmsr(IA32_PERFEVTSEL(i)) | PMC_EVTSEL_EN);
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return 0;
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}
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inline int pmc_gp_stop(uint8_t i)
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{
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if (BUILTIN_EXPECT(i > caps.gp_count, 0))
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return -EINVAL;
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wrmsr(IA32_PERFEVTSEL(i), rdmsr(IA32_PERFEVTSEL(i)) & ~PMC_EVTSEL_EN);
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return 0;
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}
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inline int pmc_ff_start(uint8_t i)
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{
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if (BUILTIN_EXPECT(i > caps.ff_count, 0))
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return -EINVAL;
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// TODO
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return 0;
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}
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inline int pmc_ff_stop(uint8_t i)
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{
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if (BUILTIN_EXPECT(i > caps.ff_count, 0))
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return -EINVAL;
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// TODO
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return 0;
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}
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inline int pmc_start_all()
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{
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if (BUILTIN_EXPECT(caps.version < 2, 0))
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return -EINVAL;
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wrmsr(MSR_PERF_GLOBAL_CTRL, -1L);
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return 0;
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}
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inline int pmc_stop_all()
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{
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if (BUILTIN_EXPECT(caps.version < 2, 0))
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return -EINVAL;
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wrmsr(MSR_PERF_GLOBAL_CTRL, 0);
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return 0;
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}
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inline int pmc_reset_all()
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{
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if (BUILTIN_EXPECT(caps.version < 2, 0))
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return -EINVAL;
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int i;
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for (i = 0; i < caps.gp_count; i++)
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pmc_gp_write(i, 0);
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for (i = 0; i < caps.ff_count; i++)
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pmc_ff_write(i, 0);
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return 0;
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}
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inline uint64_t pmc_gp_read(uint8_t i)
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{
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if (BUILTIN_EXPECT(i > caps.gp_count, 0))
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return 0;
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return rdmsr(IA32_PMC(i));
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return 0;
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}
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inline uint64_t pmc_ff_read(uint8_t i)
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{
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if (BUILTIN_EXPECT(i > caps.ff_count, 0))
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return 0;
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return rdmsr(MSR_PERF_FIXED_CTR(i));
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return 0;
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}
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inline int pmc_gp_write(uint8_t i, uint64_t val)
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{
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if (BUILTIN_EXPECT(i > caps.gp_count, 0))
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return -EINVAL;
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if (caps.version >= 2 && caps.msr & (1 << 13 /* FW_WRITE */))
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wrmsr(IA32_A_PMC(i), val);
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else
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wrmsr(IA32_PMC(i), val);
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return 0;
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}
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inline int pmc_ff_write(uint8_t i, uint64_t val)
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{
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if (BUILTIN_EXPECT(i > caps.ff_count, 0))
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return -EINVAL;
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wrmsr(MSR_PERF_FIXED_CTR(i), val);
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return 0;
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}
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