Clifford Wolf
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0bc95f1e04
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Added "yosys -D" feature
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2016-04-21 23:28:37 +02:00 |
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Clifford Wolf
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abf81d7683
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Added some missing .gitignore in manual/
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2014-12-04 13:37:58 +01:00 |
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Clifford Wolf
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b9f2127f5d
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Various documentation updates
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2014-11-08 10:59:48 +01:00 |
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Clifford Wolf
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4569a747f8
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Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
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Clifford Wolf
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e6d33513a5
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Added module->design and cell->module, wire->module pointers
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2014-07-31 14:11:39 +02:00 |
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Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
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Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
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Clifford Wolf
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a7aea17959
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Progress in presentation
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2014-06-22 12:50:29 +02:00 |