Clifford Wolf
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e9fe57c75e
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Only allow posedge/negedge with 1 bit wide signals
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2016-08-10 19:32:11 +02:00 |
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Clifford Wolf
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4056312987
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Added $anyconst and $aconst
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2016-07-27 15:41:22 +02:00 |
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Clifford Wolf
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d7763634b6
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After reading the SV spec, using non-standard predict() instead of expect()
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2016-07-21 13:34:33 +02:00 |
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Clifford Wolf
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721f1f5ecf
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Added basic support for $expect cells
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2016-07-13 16:56:17 +02:00 |
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Ruben Undheim
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178ff3e7f6
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Added support for SystemVerilog packages with localparam definitions
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2016-06-18 10:53:55 +02:00 |
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Clifford Wolf
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766032c5f8
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Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
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2016-05-27 17:55:03 +02:00 |
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Clifford Wolf
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e9ceec26ff
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fixed typos in error messages
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2016-05-27 16:37:36 +02:00 |
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Clifford Wolf
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5a09fa4553
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Fixed handling of parameters and const functions in casex/casez pattern
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2016-04-21 15:31:54 +02:00 |
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Clifford Wolf
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bcc873b805
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Fixed some visual studio warnings
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2016-02-13 17:31:24 +01:00 |
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Rick Altherr
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34969d4140
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genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()
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2016-01-31 09:20:16 -08:00 |
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Clifford Wolf
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34f2b84fb6
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Fixed handling of parameters and localparams in functions
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2015-11-11 10:54:35 +01:00 |
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Clifford Wolf
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207736b4ee
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Import more std:: stuff into Yosys namespace
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2015-10-25 19:30:49 +01:00 |
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Clifford Wolf
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924d9d6e86
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
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Clifford Wolf
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84bf862f7c
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Spell check (by Larry Doolittle)
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2015-08-14 10:56:05 +02:00 |
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Clifford Wolf
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8d6d5c30d9
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Added WORDS parameter to $meminit
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2015-07-31 10:40:09 +02:00 |
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Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
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Clifford Wolf
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422794c584
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Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
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2015-03-01 11:20:22 +01:00 |
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Clifford Wolf
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1f1deda888
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Added non-std verilog assume() statement
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2015-02-26 18:47:39 +01:00 |
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Clifford Wolf
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c2ba4fb2fd
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Convert floating point cell parameters to strings
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2015-02-18 23:35:23 +01:00 |
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Clifford Wolf
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e9368a1d7e
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Various fixes for memories with offsets
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2015-02-14 14:21:15 +01:00 |
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Clifford Wolf
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a8e9d37c14
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Creating $meminit cells in verilog front-end
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2015-02-14 10:49:30 +01:00 |
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Clifford Wolf
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234a45a3d5
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Ignore explicit assignments to constants in HDL code
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2015-02-08 00:58:03 +01:00 |
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Clifford Wolf
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c8305e3a6d
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Fixed a bug with autowire bit size
(removed leftover from when we tried to auto-size the wires)
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2015-02-08 00:48:23 +01:00 |
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Clifford Wolf
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eefe78be09
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Fixed memory->start_offset handling
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2015-01-01 12:56:01 +01:00 |
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Clifford Wolf
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137f35373f
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Changed more code to dict<> and pool<>
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2014-12-28 19:24:24 +01:00 |
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Clifford Wolf
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edb3c9d0c4
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Renamed extend() to extend_xx(), changed most users to extend_u0()
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2014-12-24 09:51:17 +01:00 |
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Clifford Wolf
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fe829bdbdc
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Added log_warning() API
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2014-11-09 10:44:23 +01:00 |
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Clifford Wolf
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4569a747f8
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Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
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Clifford Wolf
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deff416ea7
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Fixed assignment of out-of bounds array element
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2014-09-06 17:58:27 +02:00 |
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Clifford Wolf
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8927aa6148
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Removed $bu0 cell type
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2014-09-04 02:07:52 +02:00 |
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Clifford Wolf
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7bfc4ae120
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Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
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2014-08-21 12:43:51 +02:00 |
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Clifford Wolf
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64713647a9
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Improved AST ProcessGenerator performance
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2014-08-17 02:17:49 +02:00 |
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Clifford Wolf
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d491fd8c19
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Use stackmap<> in AST ProcessGenerator
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2014-08-17 00:57:24 +02:00 |
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Clifford Wolf
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83e2698e10
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AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
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2014-08-16 19:31:59 +02:00 |
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Clifford Wolf
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978a933b6a
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Added RTLIL::SigSpec::to_sigbit_map()
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2014-08-14 23:14:47 +02:00 |
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Clifford Wolf
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c83b990458
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Changed the AST genWidthRTLIL subst interface to use a std::map
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2014-08-14 23:02:07 +02:00 |
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Clifford Wolf
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b9bd22b8c8
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More cleanups related to RTLIL::IdString usage
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2014-08-02 13:19:57 +02:00 |
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Clifford Wolf
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cdae8abe16
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Renamed port access function on RTLIL::Cell, added param access functions
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2014-07-31 16:38:54 +02:00 |
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Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
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Clifford Wolf
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397b00252d
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Added $shift and $shiftx cell types (needed for correct part select behavior)
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2014-07-29 16:35:13 +02:00 |
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Clifford Wolf
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48822e79a3
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Removed left over debug code
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2014-07-28 19:38:30 +02:00 |
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Clifford Wolf
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ec58965967
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Fixed part selects of parameters
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2014-07-28 19:24:28 +02:00 |
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Clifford Wolf
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a03297a7df
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Set results of out-of-bounds static bit/part select to undef
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2014-07-28 16:09:50 +02:00 |
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Clifford Wolf
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55521c085a
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Fixed RTLIL code generator for part select of parameter
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2014-07-28 15:31:19 +02:00 |
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Clifford Wolf
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0598bc8708
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Fixed width detection for part selects
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2014-07-28 15:19:34 +02:00 |
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Clifford Wolf
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27a872d1e7
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
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Clifford Wolf
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3c45277ee0
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Added wire->upto flag for signals such as "wire [0:7] x;"
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2014-07-28 12:12:13 +02:00 |
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Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
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Clifford Wolf
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ee65dea738
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Fixed signdness detection of expressions with bit- and part-selects
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2014-07-28 10:10:08 +02:00 |
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Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
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