Clifford Wolf
bc8d94b4ae
Added "shared nodes" feature to the subcircuit library
2013-03-03 21:19:55 +01:00
Clifford Wolf
3ebc365c09
Added support for "extract_order" attribute to extract pass
2013-03-03 21:10:27 +01:00
Clifford Wolf
d4680fd5a0
Added design->select() api and use it in extract pass
2013-03-03 20:53:24 +01:00
Clifford Wolf
45bfe26f5f
Minor hotfixes (mostly gcc build fixes)
2013-03-03 13:18:37 +01:00
Clifford Wolf
65e5e1658c
Added library support to celltypes class and show pass
2013-03-03 10:36:23 +01:00
Clifford Wolf
4fcb9a7b99
Implemented general handler for selection arguments
2013-03-03 10:05:37 +01:00
Clifford Wolf
5bed90ae3a
Finished "extract -mine" feature
2013-03-02 18:57:14 +01:00
Clifford Wolf
23eb0ba8bc
Added -mine option to extract pass (not finished)
2013-03-02 16:22:37 +01:00
Clifford Wolf
a338d1a082
Added help messages for fsm_* passes
2013-03-01 12:35:12 +01:00
Clifford Wolf
f3a849512f
Added help messages to memory_* passes
2013-03-01 10:17:35 +01:00
Clifford Wolf
f952309c81
Added help messages to proc_* passes
2013-03-01 09:26:29 +01:00
Clifford Wolf
36954471a6
Added help messages for opt_* passes
2013-03-01 09:01:49 +01:00
Clifford Wolf
7fccad92f7
Added more help messages
2013-03-01 00:36:19 +01:00
Clifford Wolf
af561800ed
Added online help for "show" and "hierarchy" commands
2013-02-28 13:59:49 +01:00
Clifford Wolf
6ac41b2bb1
Added help for command line options
2013-02-28 13:13:56 +01:00
Clifford Wolf
cb592504f4
Added more help messages (extract, abc, dfflibmap)
2013-02-28 11:14:59 +01:00
Clifford Wolf
c3cc9839a9
Added port swapping and compatible types to "extract" pass
2013-02-28 10:00:42 +01:00
Clifford Wolf
08c43f27af
Added "extract -constports" feature
2013-02-27 23:39:10 +01:00
Clifford Wolf
500786af55
Fixed "extract" pass for non-optimized needles
2013-02-27 23:19:30 +01:00
Clifford Wolf
1bbc2b34c8
Added support for simple gates with one constant input to opt_const
2013-02-27 18:00:01 +01:00
Clifford Wolf
da3d55a29c
Added extract -verbose and -map ilang support
2013-02-27 17:26:32 +01:00
Clifford Wolf
f28b6aff40
Implemented basic functionality of "extract" pass
2013-02-27 16:27:20 +01:00
Clifford Wolf
c59d77aa30
Added support for constant signals in "extract" pass
2013-02-27 13:35:30 +01:00
Clifford Wolf
b02e140030
Added "extract" pass (not functional yet)
2013-02-27 13:25:18 +01:00
Clifford Wolf
a321a5c412
Moved stand-alone libs to libs/ directory and added libs/subcircuit
2013-02-27 09:32:19 +01:00
Martin Schmölzer
5a005cefe2
"fsm_export" pass: fix KISS file generation.
...
The KISS file format now follows the conventions specified in
"Logic Synthesis and Optimization Benchmarks User Guide", Version 3.0
by Saeyang Yang.
This change ensures interoperability with the "trfsmgen" program by Johann
Glaser.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
2013-02-23 18:22:19 +01:00
Martin Schmölzer
4f6cda502d
Add support for "fsm_export" synthesis attributes to fsm_export pass.
...
This allows to specify the file name for exported files directly in the HDL
source via the fsm_export=... attribute on the FSM state register.
Verilog example:
(* fsm_export="my_fsm.kiss2" *)
reg [3:0] state;
The fsm_export pass now also accepts the option "-noauto". This causes only
FSMs with the fsm_export attribute to be exported, any other FSMs are ignored.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
2013-01-08 09:43:35 +01:00
Clifford Wolf
a7988c01af
Copy attributes from state signal to fsm cell
2013-01-05 11:44:47 +01:00
Clifford Wolf
6543917fb8
added .gitignore files
2013-01-05 11:19:11 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00
