Clifford Wolf
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edf11c635a
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Assert on new logic loops in "share" pass
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2014-09-21 12:57:33 +02:00 |
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Clifford Wolf
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00964f2f61
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Initialize RTLIL::Const from std::vector<bool>
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2014-09-19 15:50:55 +02:00 |
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Clifford Wolf
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fa96cf4a16
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Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)
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2014-09-16 11:26:44 +02:00 |
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Clifford Wolf
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b470c480e9
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Added the obvious optimizations to alumacc $macc generator
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2014-09-15 12:22:03 +02:00 |
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Clifford Wolf
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2442eb3832
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Fixed monitor notifications for removed cell
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2014-09-14 17:04:39 +02:00 |
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Clifford Wolf
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7815f81c32
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Added "synth" command
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2014-09-14 16:09:06 +02:00 |
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Clifford Wolf
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fcb46138ce
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Simplified $fa undef model
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2014-09-08 16:59:39 +02:00 |
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Clifford Wolf
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af0c8873bb
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Added $lcu cell type
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2014-09-08 13:31:04 +02:00 |
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Clifford Wolf
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d46bac3305
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Added "$fa" cell type
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2014-09-08 12:15:39 +02:00 |
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Clifford Wolf
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98e6463ca7
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Added $macc eval model
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2014-09-06 19:44:28 +02:00 |
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Clifford Wolf
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fa64942018
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Added $macc SAT model
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2014-09-06 19:44:11 +02:00 |
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Clifford Wolf
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b847ec8a0b
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Added $macc cell type
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2014-09-06 15:47:46 +02:00 |
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Ruben Undheim
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79cbf9067c
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Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
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Clifford Wolf
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8927aa6148
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Removed $bu0 cell type
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2014-09-04 02:07:52 +02:00 |
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Clifford Wolf
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b9cb483f3e
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Using $pos models for $bu0
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2014-09-03 21:20:59 +02:00 |
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Clifford Wolf
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50ac284823
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Fixes in $alu SAT- and eval-models
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2014-09-03 13:39:46 +02:00 |
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Clifford Wolf
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da360771a1
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Create a default selection stack in RTLIL::Design::Design()
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2014-09-02 22:49:24 +02:00 |
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Clifford Wolf
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c38283dbd0
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Small bug fixes in $not, $neg, and $shiftx models
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2014-09-02 17:48:41 +02:00 |
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Clifford Wolf
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2fcf66b91d
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Added ConstEval model for $alu cells
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2014-09-01 16:35:46 +02:00 |
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Clifford Wolf
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bae09dca2b
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Added SAT model for $alu cells
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2014-09-01 16:35:25 +02:00 |
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Clifford Wolf
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e07698818d
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Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
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2014-09-01 11:36:02 +02:00 |
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Clifford Wolf
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83ec3fa204
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Fixed return size of const_*() eval functions
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2014-08-31 18:08:26 +02:00 |
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Clifford Wolf
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be44157c0f
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Added RTLIL::Const::size()
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2014-08-31 18:07:48 +02:00 |
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Clifford Wolf
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a1c7d4a8e2
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Added eval model for $lut cells
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2014-08-31 17:43:31 +02:00 |
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Clifford Wolf
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0b6769af3f
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Typo fixes in cell->*Param() API
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2014-08-31 17:43:31 +02:00 |
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Clifford Wolf
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8649b57b6f
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Added $lut support in test_cell, techmap, satgen
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2014-08-31 17:43:31 +02:00 |
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Clifford Wolf
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2a1b08aeb3
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Added design->scratchpad
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2014-08-30 19:37:12 +02:00 |
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Clifford Wolf
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4724d94fbc
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Added $alu cell type
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2014-08-30 18:59:05 +02:00 |
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Clifford Wolf
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dfbd7dd15a
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Fixed module->addPmux()
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2014-08-30 18:17:22 +02:00 |
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Clifford Wolf
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eda603105e
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Added is_signed argument to SigSpec.as_int() and Const.as_int()
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2014-08-24 15:14:00 +02:00 |
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Clifford Wolf
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58367cd87a
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Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
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2014-08-23 15:14:58 +02:00 |
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Clifford Wolf
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19cff41eb4
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Changed frontend-api from FILE to std::istream
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2014-08-23 15:03:55 +02:00 |
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Clifford Wolf
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5dce303a2a
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Changed backend-api from FILE to std::ostream
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2014-08-23 13:54:21 +02:00 |
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Clifford Wolf
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98442e019d
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Added emscripten (emcc) support to build system and some build fixes
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2014-08-22 16:20:22 +02:00 |
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Clifford Wolf
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a3494fa9ed
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Added "plugin" command
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2014-08-22 14:00:11 +02:00 |
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Clifford Wolf
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b37d70dfd7
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Added mod->addGate() methods for new gate types
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2014-08-19 14:26:54 +02:00 |
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Clifford Wolf
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aa7a3ed83f
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Fixed proc_{self,share}_dirname error handling
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2014-08-17 02:25:59 +02:00 |
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Clifford Wolf
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f3326a6421
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Improved sig.remove2() performance
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2014-08-17 02:16:56 +02:00 |
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Clifford Wolf
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9bacc0b54c
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Added stackmap<> container
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2014-08-17 00:56:47 +02:00 |
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Clifford Wolf
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410d043dd8
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Renamed toposort.h to utils.h
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2014-08-17 00:55:35 +02:00 |
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Clifford Wolf
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7f734ecc09
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Added module->uniquify()
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2014-08-16 23:50:36 +02:00 |
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Clifford Wolf
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47c2637a96
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Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
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2014-08-16 18:29:39 +02:00 |
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Clifford Wolf
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56a30cf42c
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Added CellTypes::cell_evaluable()
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2014-08-16 16:17:07 +02:00 |
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Clifford Wolf
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dbdf89c705
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Added log_spacer()
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2014-08-16 15:34:00 +02:00 |
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Clifford Wolf
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b64b38eea2
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Renamed $lut ports to follow A-Y naming scheme
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2014-08-15 14:18:40 +02:00 |
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Clifford Wolf
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f092b50148
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Renamed $_INV_ cell type to $_NOT_
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2014-08-15 14:11:40 +02:00 |
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Clifford Wolf
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ca87116449
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More idstring sort_by_* helpers and fixed tpl ordering in techmap
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2014-08-15 02:40:46 +02:00 |
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Clifford Wolf
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8ff71b5ae5
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Added Frontend "+/" filename syntax for files from proc_share_dir
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2014-08-15 02:08:02 +02:00 |
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Clifford Wolf
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978a933b6a
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Added RTLIL::SigSpec::to_sigbit_map()
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2014-08-14 23:14:47 +02:00 |
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Clifford Wolf
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2f44d8ccf8
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Added sig.{replace,remove,extract} variants for std::{map,set} pattern
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2014-08-14 22:32:18 +02:00 |
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