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2167 commits 1 branch 6 tags 8.6 MiB
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166 commits

Author SHA1 Message Date
Ahmed Irfan
e82e4f7df4 Update README 
pmux cell is implemented
 2015-04-03 16:45:14 +02:00
Ahmed Irfan
ea2e0297d5 separated memory next from write cell 2015-04-03 16:41:50 +02:00
Clifford Wolf
67e6dcd34a Added Verilog backend $dffsr support 2015-03-18 08:01:37 +01:00
Clifford Wolf
6c8fdb1829 Documentation for JSON format, added attributes 2015-03-06 10:21:21 +01:00
Clifford Wolf
adc12ce46e Json bugfix 2015-03-03 09:41:41 +01:00
Clifford Wolf
4fc63f27a1 Json backend improvements 2015-03-03 09:28:44 +01:00
Clifford Wolf
795a6e1d04 Added write_blif -attr 2015-03-02 23:47:45 +01:00
Clifford Wolf
8b488983d0 Added JSON backend 2015-03-02 23:30:58 +01:00
Clifford Wolf
5d4f513c3b Added $assume support to write_smt2 2015-02-26 19:02:55 +01:00
Clifford Wolf
ff3f2448b1 Minor "write_smt2" help msg change 2015-02-22 16:30:02 +01:00
Clifford Wolf
4b89dd983c Added "<mod>_a" and "<mod>_i" to write_smt2 output 2015-02-22 16:19:10 +01:00
Clifford Wolf
756b4064b2 Fixed "write_verilog -attr2comment" handling of "*/" in strings 2015-02-13 22:48:10 +01:00
Clifford Wolf
6978f3a77b Added EDIF backend support for multi-bit cell ports 2015-02-01 15:43:35 +01:00
Clifford Wolf
fb8c755726 Shorter "dump" options 2015-01-31 23:52:36 +01:00
Clifford Wolf
2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf
43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf
146f769bee Cosmetic changes in verilog output format 2015-01-02 22:57:08 +01:00
Clifford Wolf
eefe78be09 Fixed memory->start_offset handling 2015-01-01 12:56:01 +01:00
Clifford Wolf
9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf
a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf
e8c12e5f0c Various fixes and improvements in "write_smt2 -bv" 2014-12-25 20:28:34 +01:00
Clifford Wolf
68233baa1f Various fixes and improvements in write_smt2 2014-12-25 17:52:31 +01:00
Clifford Wolf
95f17dbab0 Added support for most BV cell types to write_smt2 2014-12-25 15:37:02 +01:00
Clifford Wolf
1c3d51375f Added "write_smt2 -bv" and other write_smt2 improvements 2014-12-25 13:30:20 +01:00
Clifford Wolf
e548483c91 Added write_smt2 (only gate level logic supported so far) 2014-12-24 16:17:57 +01:00
Clifford Wolf
edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf
5df192e71c Added $dffe support to write_verilog 2014-12-20 00:03:20 +01:00
Clifford Wolf
30de490d86 Fixed another bug in write_blif handling of $lut cells 2014-12-19 17:54:44 +01:00
Clifford Wolf
b95051fb70 Fixed writing of $lut cells in BLIF backend 2014-12-17 11:13:57 +01:00
Clifford Wolf
e01254d824 Added "write_blif -undef" and support for special "-" true/false/undef type 2014-12-14 18:00:38 +01:00
Clifford Wolf
59d11978fc Added "write_blif -blackbox" 
based on code by Eddie Hung from
https://github.com/eddiehung/yosys/commit/1e481661cb4a4
 2014-12-14 17:45:03 +01:00
Clifford Wolf
32dce4a870 Added "blif -unbuf" feature 2014-12-14 17:37:46 +01:00
Clifford Wolf
fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf
461594bb83 Fixed generation of temp names in verilog backend 2014-11-07 14:40:06 +01:00
Clifford Wolf
4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf
f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Ahmed Irfan
d3c67ad9b6 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc
 2014-09-22 11:35:04 +02:00
Clifford Wolf
309623ff17 Sorting of object names in ilang backend 2014-09-19 15:50:34 +02:00
ahmedirfan1983
b783dbe148 fixed memory next issue, when same memory is written in different case statement 
fixed reduce_xnor, logic_not bug translation bug
 2014-09-18 11:19:48 +02:00
Clifford Wolf
9329a76818 Various bug fixes (related to $macc model testing) 2014-09-06 20:30:46 +02:00
Ruben Undheim
79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf
8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf
b9cb483f3e Using $pos models for $bu0 2014-09-03 21:20:59 +02:00
Ahmed Irfan
2446b6fbef added $pmux cell translation 2014-09-02 14:47:51 +02:00
Clifford Wolf
e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf
19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf
5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf
f82c978e08 Fixed AOI/OAI expr handling in verilog backend 2014-08-16 22:05:09 +02:00
Clifford Wolf
47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf
b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00