Clifford Wolf
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fcbda07411
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Improved maccmap tree bit packing
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2014-09-15 12:00:19 +02:00 |
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Clifford Wolf
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2cbdbaad1f
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Fixed wreduce $shiftx handling
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2014-09-15 11:29:09 +02:00 |
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Clifford Wolf
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7e156a5419
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Fixed techmap_wrap for techmap_celltype
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2014-09-14 15:34:36 +02:00 |
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Clifford Wolf
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014bb34e0e
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Various fixes/cleanups in alumacc and maccmap
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2014-09-14 14:49:53 +02:00 |
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Clifford Wolf
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124e759280
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Added techmap_wrap attribute
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2014-09-14 14:49:26 +02:00 |
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Clifford Wolf
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b34ca15185
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alumacc fix for $pos cells
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2014-09-14 14:00:14 +02:00 |
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Clifford Wolf
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0df1d9ad72
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Extract $alu cells in alumacc
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2014-09-14 13:23:44 +02:00 |
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Clifford Wolf
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7b16c63101
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Merge $macc cells in alumacc pass
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2014-09-14 11:21:37 +02:00 |
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Clifford Wolf
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0b72f0acb1
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Basic $macc extract in alumacc
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2014-09-14 10:45:28 +02:00 |
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Clifford Wolf
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ff157fb74f
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alumacc skeleton
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2014-09-14 10:02:00 +02:00 |
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Clifford Wolf
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aab0e3bf70
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Cleanup in wreduce
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2014-09-14 10:01:30 +02:00 |
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Clifford Wolf
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af0c8873bb
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Added $lcu cell type
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2014-09-08 13:31:04 +02:00 |
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Clifford Wolf
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d46bac3305
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Added "$fa" cell type
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2014-09-08 12:15:39 +02:00 |
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Clifford Wolf
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1a88e47396
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Trim msb/lsb zero bits from full adder in maccmap
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2014-09-08 11:21:58 +02:00 |
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Clifford Wolf
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6747a7047e
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Added "test_cell -const"
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2014-09-08 11:12:39 +02:00 |
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Clifford Wolf
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c50b841b29
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Added 'techmap_maccmap' techmap attribute
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2014-09-07 18:23:37 +02:00 |
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Clifford Wolf
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015dcdc84c
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Added "maccmap" command
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2014-09-07 18:23:04 +02:00 |
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Clifford Wolf
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15b3c54fea
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Added "test_cell -nosat"
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2014-09-07 17:05:41 +02:00 |
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Clifford Wolf
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9329a76818
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Various bug fixes (related to $macc model testing)
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2014-09-06 20:30:46 +02:00 |
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Clifford Wolf
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fa64942018
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Added $macc SAT model
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2014-09-06 19:44:11 +02:00 |
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Clifford Wolf
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b847ec8a0b
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Added $macc cell type
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2014-09-06 15:47:46 +02:00 |
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Clifford Wolf
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34af6a1303
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-09-06 11:46:44 +02:00 |
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Clifford Wolf
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e1743b3bac
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Added "test_cell -script"
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2014-09-06 11:46:07 +02:00 |
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Ruben Undheim
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79cbf9067c
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Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
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Clifford Wolf
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f5a40e7043
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Fixed "opt_const -fine" for $pos cells
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2014-09-04 08:55:58 +02:00 |
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Clifford Wolf
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8927aa6148
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Removed $bu0 cell type
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2014-09-04 02:07:52 +02:00 |
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Clifford Wolf
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5733f4a39d
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Fixed "test_cells -vlog"
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2014-09-03 13:43:37 +02:00 |
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Clifford Wolf
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f1869667ca
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Improvements in "test_cell -vlog"
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2014-09-02 23:21:15 +02:00 |
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Clifford Wolf
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66bf2bb92e
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Added test_cell -vlog
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2014-09-02 22:49:43 +02:00 |
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Clifford Wolf
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acd7a99aef
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Added SAT testing to test_cell eval stage
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2014-09-02 17:28:13 +02:00 |
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Clifford Wolf
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37fe7c7bdf
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Removed references to yosys-svgviewer from docs
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2014-09-02 04:03:06 +02:00 |
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Clifford Wolf
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9f00a0cd2d
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Using "xdot" instead of "yosys-svgviewer" in show command
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2014-09-02 03:28:46 +02:00 |
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Clifford Wolf
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630befdf6d
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Added $alu support to test_cell
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2014-09-01 16:36:04 +02:00 |
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Clifford Wolf
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c7f81e4e49
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Added "test_cell -simlib -v"
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2014-09-01 15:37:21 +02:00 |
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Clifford Wolf
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826fdb34d8
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Added "techmap -autoproc"
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2014-09-01 15:36:29 +02:00 |
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Clifford Wolf
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27a1bfbec6
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Fixes in old SAT example.ys
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2014-09-01 11:45:47 +02:00 |
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Clifford Wolf
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d5148f2e01
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Moved "share" and "wreduce" to passes/opt/
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2014-09-01 11:45:26 +02:00 |
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Clifford Wolf
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e07698818d
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Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
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2014-09-01 11:36:02 +02:00 |
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Clifford Wolf
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e3664066d5
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Added eval testing to test_cell
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2014-08-31 18:08:42 +02:00 |
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Clifford Wolf
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8649b57b6f
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Added $lut support in test_cell, techmap, satgen
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2014-08-31 17:43:31 +02:00 |
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Clifford Wolf
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2a1b08aeb3
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Added design->scratchpad
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2014-08-30 19:37:12 +02:00 |
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Clifford Wolf
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6ff46323a3
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Improved write address decoder generation memory_map
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2014-08-30 18:18:15 +02:00 |
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Clifford Wolf
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66763fad4e
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Using worker class in memory_map
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2014-08-30 17:39:08 +02:00 |
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Clifford Wolf
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3a7d5d188d
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Don't change existing binary FSM encoding if it is already optimal
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2014-08-30 14:43:06 +02:00 |
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Clifford Wolf
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f910481f35
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Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
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2014-08-30 14:34:49 +02:00 |
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Clifford Wolf
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ab019b0bd5
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Improved handling of $pmux cells in fsm_extract
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2014-08-30 14:11:57 +02:00 |
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Clifford Wolf
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d148b0af0d
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Fixed inserting of Q-inverters in dfflibmap
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2014-08-27 19:44:12 +02:00 |
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Clifford Wolf
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084685f480
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Implemented "rename -enumerate -pattern"
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2014-08-26 12:51:08 +02:00 |
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Clifford Wolf
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7bbbe3580d
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Optimize shift ops with constant rhs in opt_const
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2014-08-24 17:08:43 +02:00 |
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Clifford Wolf
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641501203c
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Added some additional log messages to opt_const
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2014-08-24 17:08:43 +02:00 |
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