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  • fa92722358 Added miter command Clifford Wolf 2014-02-01 10:35:56 +01:00
  • 1c8f6f21b4 Progress on presentation Clifford Wolf 2014-01-31 12:48:31 +01:00
  • ed8ad99960 More changes to techlibs/common/simlib.v for LEC Clifford Wolf 2014-01-31 11:21:29 +01:00
  • 36a808c572 presentation progress Clifford Wolf 2014-01-30 15:25:09 +01:00
  • 4df7e03ec9 Bugfix in name resolution with generate blocks Clifford Wolf 2014-01-30 14:52:46 +01:00
  • 672229eda5 Added yosys -H for command list Clifford Wolf 2014-01-30 12:32:59 +01:00
  • 34b39ec28a presentation progress Clifford Wolf 2014-01-29 15:56:58 +01:00
  • cbe77bf844 presentation progress Clifford Wolf 2014-01-29 12:15:38 +01:00
  • aceab5fc08 Tiny change in example script in README Clifford Wolf 2014-01-29 11:11:10 +01:00
  • 96084e9864 Added -h command line option Clifford Wolf 2014-01-29 11:10:39 +01:00
  • 6a7d7e847d Added test comments to techlibs/cmos/cmos_cells.lib Clifford Wolf 2014-01-29 10:51:02 +01:00
  • c46b23ab23 Updated ABC to hg rev e6b09e1 Clifford Wolf 2014-01-29 10:50:15 +01:00
  • 375c4dddc1 Added read_verilog -icells option Clifford Wolf 2014-01-29 00:59:28 +01:00
  • a86f33653d Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal) Clifford Wolf 2014-01-29 00:36:03 +01:00
  • 961b791272 presentation progress Clifford Wolf 2014-01-28 20:28:22 +01:00
  • 2cb47355d4 Renamed manual/FILES_* directories Clifford Wolf 2014-01-28 06:55:47 +01:00
  • 842ca2f011 Progress on presentation Clifford Wolf 2014-01-28 06:51:50 +01:00
  • a3ac6b6f47 Progress on presentation Clifford Wolf 2014-01-27 20:42:35 +01:00
  • fb4c3dff33 Added first presentation slides Clifford Wolf 2014-01-27 17:08:19 +01:00
  • fa103e55ad Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys Clifford Wolf 2014-01-26 02:29:19 +01:00
  • fd6ca84f3c Merge pull request #21 from hansiglaser/master Clifford Wolf 2014-01-25 17:28:17 -08:00
  • e9a2094774 enabled multiple "-map" for the extract pass Johann Glaser 2014-01-25 21:11:34 +01:00
  • f13b3518aa beautified write_intersynth Johann Glaser 2014-01-25 20:16:38 +01:00
  • 0325efe172 root bug corrected Ahmed Irfan 2014-01-25 19:33:24 +01:00
  • c1ed2607fb Added support for // comments in liberty parser Clifford Wolf 2014-01-25 06:32:16 +01:00
  • a139b49401 Merge branch 'btor' Clifford Wolf 2014-01-24 23:44:46 +01:00
  • 137742786e removed regex include Ahmed Irfan 2014-01-24 18:04:37 +01:00
  • 2e44b1b73a merged clifford changes + removed regex Ahmed Irfan 2014-01-24 17:35:42 +01:00
  • 210dda286f Use techmap -share_map in btor scripts Clifford Wolf 2014-01-24 15:52:16 +01:00
  • 6804edd5d4 Moved btor scripts to backends/btor/ Clifford Wolf 2014-01-24 15:48:07 +01:00
  • da26bb4378 Restored Makefile Clifford Wolf 2014-01-24 15:47:09 +01:00
  • ec167350b4 Restored IdString::check() Clifford Wolf 2014-01-24 15:46:41 +01:00
  • d8300d1fb8 Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor Clifford Wolf 2014-01-24 15:43:42 +01:00
  • 0b47d907d3 Fixed handling of unsized constants in verilog frontend Clifford Wolf 2014-01-24 15:05:24 +01:00
  • 761b8f99d7 minor change in script Ahmed Irfan 2014-01-24 15:00:43 +01:00
  • 9d07d83c5a Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor Ahmed Irfan 2014-01-22 10:45:21 +01:00
  • 88fbdd4916 Fixed algorithmic complexity of AST simplification of long expressions Clifford Wolf 2014-01-20 20:25:20 +01:00
  • aa3cb20e1e slice bug corrected Ahmed Irfan 2014-01-20 18:35:52 +01:00
  • c347f2825f assert feature Ahmed Irfan 2014-01-20 10:45:02 +01:00
  • b7adf4c7a0 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor Ahmed Irfan 2014-01-20 09:58:04 +01:00
  • 32a91458a7 Added hilomap command Clifford Wolf 2014-01-19 21:58:58 +01:00
  • 03a876c7e8 Added sat -tempinduc and sat -prove-asserts Clifford Wolf 2014-01-19 15:38:23 +01:00
  • c36bac0e10 Added $assert support to satgen Clifford Wolf 2014-01-19 15:37:56 +01:00
  • 1e67099b77 Added $assert cell Clifford Wolf 2014-01-19 14:03:40 +01:00
  • 9a1eb45c75 Added Verilog parser support for asserts Clifford Wolf 2014-01-19 04:18:22 +01:00
  • 234d0d0e1c script added Ahmed Irfan 2014-01-18 21:54:52 +01:00
  • 90483f489b Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor Ahmed Irfan 2014-01-18 19:45:16 +01:00
  • 3d7a1491aa Fixed $lut simlib model for a wider range of tools Clifford Wolf 2014-01-18 19:27:16 +01:00
  • 13359d65ba Fixed parsing of verilog macros at end of line Clifford Wolf 2014-01-18 19:22:20 +01:00
  • 2fbaaaca7a More changes to simlib to make it friendlier to a wider range of tools Clifford Wolf 2014-01-18 19:13:43 +01:00
  • 4a9e133fab Fixed a type in $mem model in simlib.v Clifford Wolf 2014-01-18 18:54:50 +01:00
  • b281e13263 Merge branch 'master' of https://github.com/ahmedirfan1983/yosys Ahmed Irfan 2014-01-18 18:11:26 +01:00
  • 1dd797ab09 Merge branch 'master' of https://github.com/cliffordwolf/yosys Ahmed Irfan 2014-01-18 18:10:31 +01:00
  • da8af91552 pmux2mux Ahmed Irfan 2014-01-18 17:29:55 +01:00
  • bef17eeb10 Removed cases of trailing comma in stdcells.v Clifford Wolf 2014-01-18 15:36:17 +01:00
  • 5b96675696 Added $bu0 cell to simlib.v Clifford Wolf 2014-01-18 15:35:15 +01:00
  • 839af272ad Improved setundef random number generator Clifford Wolf 2014-01-18 02:56:36 +01:00
  • 091d9abc3e Added setundef command Clifford Wolf 2014-01-17 23:14:36 +01:00
  • 548d5aafa4 Some improvements in log_dump_val_worker() templates Clifford Wolf 2014-01-17 23:14:17 +01:00
  • db9cf544b8 Added techlibs/common/pmux2mux.v Clifford Wolf 2014-01-17 20:06:15 +01:00
  • 9a689f33a5 verilog default options pull shift operator width issues Ahmed Irfan 2014-01-17 19:32:35 +01:00
  • fc3f2961be Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor Ahmed Irfan 2014-01-17 19:07:41 +01:00
  • f2ee57f798 Merge pull request #4 from cliffordwolf/master Ahmed Irfan 2014-01-17 10:07:05 -08:00
  • 6170cfe9cd Added verilog_defaults command Clifford Wolf 2014-01-17 17:22:29 +01:00
  • 2e370d5a2f Added support for $adff with undef data inputs to opt_rmdff Clifford Wolf 2014-01-17 16:42:40 +01:00
  • 651ce67d97 Added select -assert-none and -assert-any Clifford Wolf 2014-01-17 16:34:50 +01:00
  • be7707c5cf Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor Ahmed Irfan 2014-01-17 10:50:59 +01:00
  • 2d7bcaf2f2 Merge pull request #3 from cliffordwolf/master Ahmed Irfan 2014-01-17 01:48:55 -08:00
  • f3154f5694 Added automatic memid generation to memory_unpack command Clifford Wolf 2014-01-17 00:15:15 +01:00
  • 4d8318ad1b Added memory_unpack command Clifford Wolf 2014-01-17 00:05:02 +01:00
  • c7a2e582aa slice error corrected Ahmed Irfan 2014-01-16 20:16:01 +01:00
  • 3a1490888d width issues dff cell for more than one registers Ahmed Irfan 2014-01-15 17:36:33 +01:00
  • 8661626157 Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor Ahmed Irfan 2014-01-15 11:26:44 +01:00
  • 66198d8591 Merge pull request #2 from cliffordwolf/master Ahmed Irfan 2014-01-15 02:20:34 -08:00
  • 11c7df40c3 Merge pull request #20 from mschmoelzer/master Clifford Wolf 2014-01-14 11:51:28 -08:00
  • aa17f16fec Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3)) Martin Schmölzer 2014-01-14 20:12:45 +01:00
  • 0c5b1f32d4 Added hierarchy -libdir option Clifford Wolf 2014-01-14 19:28:20 +01:00
  • 9a00980129 renamed LibertyParer to LibertyParser Clifford Wolf 2014-01-14 18:57:47 +01:00
  • c1da7661a5 Added "+" to list of liberty token characters Clifford Wolf 2014-01-14 18:56:29 +01:00
  • 661b5a993e BTOR backend Ahmed Irfan 2014-01-14 12:03:53 +01:00
  • 1091c24d00 Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor Ahmed Irfan 2014-01-14 11:25:06 +01:00
  • b4ce7fee06 Merge pull request #1 from cliffordwolf/master Ahmed Irfan 2014-01-14 02:22:10 -08:00
  • 54275c61ee Added "opt_const -mux_undef" Clifford Wolf 2014-01-14 11:10:29 +01:00
  • a3d94bf888 Fixed typo in frontends/ast/simplify.cc Clifford Wolf 2014-01-12 21:04:42 +01:00
  • bc541b47ea Improved performance of freduce input cone reduction Clifford Wolf 2014-01-04 13:10:51 +01:00
  • b791af174e Improved freduce performance on const signals Clifford Wolf 2014-01-04 00:06:36 +01:00
  • 10f45b8c8e Performance improvements in freduce pass Clifford Wolf 2014-01-03 21:29:28 +01:00
  • c44e1bec6d More freduce cleanups Clifford Wolf 2014-01-03 18:17:28 +01:00
  • 8f11eaaca6 Added updating of RTLIL::autoidx to ilang frontend Clifford Wolf 2014-01-03 17:51:05 +01:00
  • 03f0ab9de2 Cleanups in freduce command Clifford Wolf 2014-01-03 17:50:39 +01:00
  • 7354a1718e Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux Clifford Wolf 2014-01-03 17:30:50 +01:00
  • 8a8d444648 Tiny cleanup in proc_mux.cc Clifford Wolf 2014-01-03 16:54:59 +01:00
  • 09f16c9d0c splitnet -driver feature Ahmed Irfan 2014-01-03 16:54:32 +01:00
  • 60fbca9970 Added "splitnets -driver" Clifford Wolf 2014-01-03 14:01:06 +01:00
  • bf5e5429c1 Use selection in freduce command Clifford Wolf 2014-01-03 13:15:11 +01:00
  • c3e9f0712f Another small freduce cleanup/bugfix Clifford Wolf 2014-01-03 12:34:18 +01:00
  • 914e208aa3 Added "connect" command Clifford Wolf 2014-01-03 12:33:00 +01:00
  • 06482c046b Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor Ahmed Irfan 2014-01-03 10:54:54 +01:00
  • 5da334fc2e makefile Ahmed Irfan 2014-01-03 10:54:30 +01:00
  • ffd768ce86 btor Ahmed Irfan 2014-01-03 10:52:44 +01:00