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added SDSoC platform for 7020

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This commit is contained in:
Steffen Vogel 2016-03-15 02:15:18 +01:00
parent b55b6ea2fa
commit 9ff70b5848
190 changed files with 295893 additions and 0 deletions
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sdsoc-platform/zturn-7z020/arm-xilinx-eabi/lib/libxil.a Normal file
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sdsoc-platform/zturn-7z020/arm-xilinx-eabi/lscript.ld Normal file
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/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: Xilinx EDK 2013.4 EDK_2013.4.20131205 */
/* */
/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x40000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x8000000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x3FF00000
ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
*(.vectors)
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_0_S_AXI_BASEADDR
.init : {
KEEP (*(.init))
} > ps7_ddr_0_S_AXI_BASEADDR
.fini : {
KEEP (*(.fini))
} > ps7_ddr_0_S_AXI_BASEADDR
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.got : {
*(.got)
} > ps7_ddr_0_S_AXI_BASEADDR
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_0_S_AXI_BASEADDR
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_0_S_AXI_BASEADDR
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_0_S_AXI_BASEADDR
_end = .;
}

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sdsoc-platform/zturn-7z020/boot/fsbl.elf Normal file
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sdsoc-platform/zturn-7z020/boot/generic.readme Normal file
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-= SD card boot image =-
Platform: <platform>
Application: <elf>
1. Copy the contents of this directory to an SD card
2. Set boot mode to SD
Jumper J1 NC
Jumper J2 1-2
3. Insert SD card and turn board on

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sdsoc-platform/zturn-7z020/boot/standalone.bif Normal file
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/* standalone */
the_ROM_image:
{
[bootloader]<boot/fsbl.elf>
<bitstream>
<elf>
}

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sdsoc-platform/zturn-7z020/hardware/prebuilt/bitstream.bit Normal file
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sdsoc-platform/zturn-7z020/hardware/prebuilt/export/z_turn20.hdf Normal file
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sdsoc-platform/zturn-7z020/hardware/prebuilt/hwcf/apsys_0.xml Normal file
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<?xml version="1.0"?>
<cf:model cf:partition="0" cf:prefix="_p0_" cf:name="top" xd:type="design" xmlns:xd="http://www.xilinx.com/xd" xmlns:cf="http://www.xilinx.com/connections">
<cf:block cf:name="hwblk_mmult">
<cf:port cf:name="cmd_mmult" cf:portType="stream" cf:direction="in"/>
<cf:port cf:name="A" cf:portType="stream" cf:direction="in"/>
<cf:port cf:name="B" cf:portType="stream" cf:direction="in"/>
<cf:port cf:name="C" cf:portType="stream" cf:direction="out"/>
</cf:block>
<cf:block cf:name="swblk_mmult">
<cf:port cf:name="cmd_mmult" cf:portType="stream" cf:direction="out"/>
<cf:port cf:name="A" cf:portType="stream" cf:direction="out"/>
<cf:port cf:name="B" cf:portType="stream" cf:direction="out"/>
<cf:port cf:name="C" cf:portType="stream" cf:direction="in"/>
</cf:block>
<cf:comp cf:name="datamover_0" xd:componentRef="axi_dma" xd:clockId="2"/>
<cf:comp cf:name="datamover_1" xd:componentRef="axi_dma" xd:clockId="2"/>
<cf:comp cf:name="datamover_2" xd:componentRef="axi_dma" xd:clockId="2"/>
<cf:comp cf:name="z_turn20" xd:componentRef="z_turn20" xd:clockId="2"/>
<cf:comp cf:name="mmult_0" xd:componentRef="mmult" xd:clockId="3"/>
<cf:instance cf:name="hwinst_mmult_0" cf:blockName="hwblk_mmult" cf:compName="mmult_0">
<cf:portMap cf:blockPort="cmd_mmult" cf:compPort="ap_ctrl" xd:register="0x28"/>
<cf:portMap cf:blockPort="A" cf:compPort="A"/>
<cf:portMap cf:blockPort="B" cf:compPort="B"/>
<cf:portMap cf:blockPort="C" cf:compPort="C"/>
</cf:instance>
<cf:instance cf:name="swinst_mmult_0" cf:blockName="swblk_mmult" cf:compName="z_turn20">
<cf:portMap cf:blockPort="cmd_mmult" cf:compPort="M_AXI_GP1"/>
<cf:portMap cf:blockPort="A" cf:compPort="S_AXI_ACP"/>
<cf:portMap cf:blockPort="B" cf:compPort="S_AXI_ACP"/>
<cf:portMap cf:blockPort="C" cf:compPort="S_AXI_ACP"/>
</cf:instance>
<cf:connection cf:srcInst="swinst_mmult_0" cf:srcPort="cmd_mmult" cf:dstInst="hwinst_mmult_0" cf:dstPort="cmd_mmult">
<cf:dataMover cf:compName="z_turn20" cf:softwareLib="axi_lite"/>
</cf:connection>
<cf:connection cf:srcInst="swinst_mmult_0" cf:srcPort="A" cf:dstInst="hwinst_mmult_0" cf:dstPort="A">
<cf:dataMover cf:compName="datamover_1" cf:softwareLib="axi_dma_simple"/>
</cf:connection>
<cf:connection cf:srcInst="swinst_mmult_0" cf:srcPort="B" cf:dstInst="hwinst_mmult_0" cf:dstPort="B">
<cf:dataMover cf:compName="datamover_0" cf:softwareLib="axi_dma_simple"/>
</cf:connection>
<cf:connection cf:srcInst="hwinst_mmult_0" cf:srcPort="C" cf:dstInst="swinst_mmult_0" cf:dstPort="C">
<cf:dataMover cf:compName="datamover_2" cf:softwareLib="axi_dma_simple"/>
</cf:connection>
</cf:model>

4
sdsoc-platform/zturn-7z020/hardware/prebuilt/hwcf/partitions.xml Normal file
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<?xml version="1.0"?>
<xd:XidanePass xd:num_partitions="1" xmlns:xd="http://www.xilinx.com/xd">
<xd:file xd:partition="0" xd:name="apsys_0.xml"/>
</xd:XidanePass>

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sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/devreg.c Normal file
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/* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/devreg.c */
#include "cf_lib.h"
#include "cf_request.h"
#include "devreg.h"
#include "stdio.h" // for getting printf
#include "xlnk_core_cf.h"
#include "accel_info.h"
#include "axi_dma_simple_dm.h"
#include "axi_lite_dm.h"
axi_dma_simple_info_t _p0_datamover_0 = {
.device_id = 0,
.phys_base_addr = 0x80400000,
.addr_range = 0x10000,
.dir = XLNK_DMA_TO_DEV,
};
axi_dma_simple_info_t _p0_datamover_1 = {
.device_id = 1,
.phys_base_addr = 0x80410000,
.addr_range = 0x10000,
.dir = XLNK_DMA_TO_DEV,
};
axi_dma_simple_info_t _p0_datamover_2 = {
.device_id = 2,
.phys_base_addr = 0x80420000,
.addr_range = 0x10000,
.dir = XLNK_DMA_FROM_DEV,
};
accel_info_t _sds__p0_mmult_0 = {
.device_id = 3,
.phys_base_addr = 0x83c00000,
.addr_range = 0x10000,
.ip_type = "axis_acc_adapter"
};
void _p0_cf_register(int first)
{
int xlnk_init_done = cf_xlnk_open(first);
if (xlnk_init_done == 0) {
axi_dma_simple_register(&_p0_datamover_0);
axi_dma_simple_register(&_p0_datamover_1);
axi_dma_simple_register(&_p0_datamover_2);
accel_register(&_sds__p0_mmult_0);
cf_xlnk_init(first);
}
else if (xlnk_init_done <0) {
fprintf(stderr, "ERROR: unable to open xlnk %d\n", xlnk_init_done);
}
else {
}
}
void _p0_cf_unregister(int last)
{
axi_dma_simple_unregister(&_p0_datamover_0);
axi_dma_simple_unregister(&_p0_datamover_1);
axi_dma_simple_unregister(&_p0_datamover_2);
accel_unregister(&_sds__p0_mmult_0);
xlnkClose(last,NULL);
}

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sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/devreg.h Normal file
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#ifndef _SDI_DEVREG_H
#define _SDI_DEVREG_H
/* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/devreg.h */
#ifdef __cplusplus
extern "C" {
#endif
void _p0_cf_register(int);
void _p0_cf_unregister(int);
#ifdef __cplusplus
};
#endif
#endif /* _SDI_DEVREG_H_ */

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sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/portinfo.c Normal file
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/* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/portinfo.c */
#include "cf_lib.h"
#include "cf_request.h"
#include "devreg.h"
#include "portinfo.h"
#include "stdio.h" // for printf
#include "xlnk_core_cf.h"
#include "accel_info.h"
#include "axi_dma_simple_dm.h"
#include "axi_lite_dm.h"
extern axi_dma_simple_info_t _p0_datamover_0;
extern axi_dma_simple_info_t _p0_datamover_1;
extern axi_dma_simple_info_t _p0_datamover_2;
extern accel_info_t _sds__p0_mmult_0;
axi_lite_info_t _p0_swinst_mmult_0_cmd_mmult_info = {
.accel_info = &_sds__p0_mmult_0,
.reg_name = "0x28"
};
axi_dma_simple_channel_info_t _p0_swinst_mmult_0_A_info = {
.dma_info = &_p0_datamover_1,
.in_use = 0,
.needs_cache_flush_invalidate = 0
};
axi_dma_simple_channel_info_t _p0_swinst_mmult_0_B_info = {
.dma_info = &_p0_datamover_0,
.in_use = 0,
.needs_cache_flush_invalidate = 0
};
axi_dma_simple_channel_info_t _p0_swinst_mmult_0_C_info = {
.dma_info = &_p0_datamover_2,
.in_use = 0,
.needs_cache_flush_invalidate = 0
};
struct _p0_swblk_mmult _p0_swinst_mmult_0 = {
.cmd_mmult = { .base = {
.channel_info = &_p0_swinst_mmult_0_cmd_mmult_info,
.open_i = &axi_lite_open,
.close_i = &axi_lite_close },
.send_i = &axi_lite_send },
.A = { .base = {
.channel_info = &_p0_swinst_mmult_0_A_info,
.open_i = &axi_dma_simple_open,
.close_i = &axi_dma_simple_close },
.send_i = &axi_dma_simple_send_i },
.B = { .base = {
.channel_info = &_p0_swinst_mmult_0_B_info,
.open_i = &axi_dma_simple_open,
.close_i = &axi_dma_simple_close },
.send_i = &axi_dma_simple_send_i },
.C = { .base = {
.channel_info = &_p0_swinst_mmult_0_C_info,
.open_i = &axi_dma_simple_open,
.close_i = &axi_dma_simple_close },
.receive_ref_i = 0,
.receive_i = &axi_dma_simple_recv_i },
};
void _p0_cf_open_port (cf_port_base_t *port)
{
port->open_i(port, NULL);
}
void _p0_cf_framework_open(int first)
{
cf_context_init();
xlnkCounterMap();
_p0_cf_register(first);
cf_get_current_context();
accel_open(&_sds__p0_mmult_0);
_p0_cf_open_port( &_p0_swinst_mmult_0.cmd_mmult.base );
_p0_cf_open_port( &_p0_swinst_mmult_0.A.base );
_p0_cf_open_port( &_p0_swinst_mmult_0.B.base );
_p0_cf_open_port( &_p0_swinst_mmult_0.C.base );
}
void _p0_cf_framework_close(int last)
{
cf_close_i( &_p0_swinst_mmult_0.cmd_mmult, NULL);
cf_close_i( &_p0_swinst_mmult_0.A, NULL);
cf_close_i( &_p0_swinst_mmult_0.B, NULL);
cf_close_i( &_p0_swinst_mmult_0.C, NULL);
accel_close(&_sds__p0_mmult_0);
_p0_cf_unregister(last);
}
#define TOTAL_PARTITIONS 1
int current_partition_num = 0;
struct {
void (*open)(int);
void (*close)(int);
}
_ptable[TOTAL_PARTITIONS] = {
{.open = &_p0_cf_framework_open, .close= &_p0_cf_framework_close},
};
void switch_to_next_partition(int partition_num)
{
#ifdef __linux__
if (current_partition_num != partition_num) {
_ptable[current_partition_num].close(0);
char buf[128];
sprintf(buf, "cat /mnt/_sds/_p%d_.bin > /dev/xdevcfg", partition_num);
system(buf);
_ptable[partition_num].open(0);
current_partition_num = partition_num;
}
#endif
}
void init_first_partition() __attribute__ ((constructor));
void close_last_partition() __attribute__ ((destructor));
void init_first_partition()
{
current_partition_num = 0;
_ptable[current_partition_num].open(1);
}
void close_last_partition()
{
#ifdef PERF_EST
apf_perf_estimation_exit();
#endif
_ptable[current_partition_num].close(1);
current_partition_num = 0;
}

31
sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/portinfo.h Normal file
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#ifndef _SDI_PORTINFO_H
#define _SDI_PORTINFO_H
/* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/portinfo.h */
#ifdef __cplusplus
extern "C" {
#endif
struct _p0_swblk_mmult {
cf_port_send_t cmd_mmult;
cf_port_send_t A;
cf_port_send_t B;
cf_port_receive_t C;
};
extern struct _p0_swblk_mmult _p0_swinst_mmult_0;
void _p0_cf_framework_open(int);
void _p0_cf_framework_close(int);
#ifdef __cplusplus
};
#endif
#ifdef __cplusplus
extern "C" {
#endif
void switch_to_next_partition(int);
void init_first_partition();
void close_last_partition();
#ifdef __cplusplus
};
#endif /* extern "C" */
#endif /* _SDI_PORTINFO_H_ */

203
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/constrs_1/new/system.xdc Normal file
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set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[24]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[23]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[21]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[20]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[19]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[18]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[17]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[16]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[24]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[23]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[21]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[20]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[19]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[18]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[17]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[16]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[0]}]
set_property PACKAGE_PIN T11 [get_ports {IO_B34_LP[1]}]
set_property PACKAGE_PIN T10 [get_ports {IO_B34_LN[1]}]
set_property PACKAGE_PIN T12 [get_ports {IO_B34_LP[2]}]
set_property PACKAGE_PIN U12 [get_ports {IO_B34_LN[2]}]
set_property PACKAGE_PIN U13 [get_ports {IO_B34_LP[3]}]
set_property PACKAGE_PIN V13 [get_ports {IO_B34_LN[3]}]
set_property PACKAGE_PIN V12 [get_ports {IO_B34_LP[4]}]
set_property PACKAGE_PIN W13 [get_ports {IO_B34_LN[4]}]
set_property PACKAGE_PIN T14 [get_ports {IO_B34_LP[5]}]
set_property PACKAGE_PIN T15 [get_ports {IO_B34_LN[5]}]
set_property PACKAGE_PIN T16 [get_ports {LCD_DATA[0]}]
set_property PACKAGE_PIN U17 [get_ports {LCD_DATA[1]}]
set_property PACKAGE_PIN V15 [get_ports {LCD_DATA[2]}]
set_property PACKAGE_PIN W15 [get_ports {LCD_DATA[3]}]
set_property PACKAGE_PIN U18 [get_ports {LCD_DATA[4]}]
set_property PACKAGE_PIN U19 [get_ports {LCD_DATA[5]}]
set_property PACKAGE_PIN N18 [get_ports {LCD_DATA[6]}]
set_property PACKAGE_PIN P19 [get_ports {LCD_DATA[7]}]
set_property PACKAGE_PIN N20 [get_ports {LCD_DATA[8]}]
set_property PACKAGE_PIN P20 [get_ports {LCD_DATA[9]}]
set_property PACKAGE_PIN T20 [get_ports {LCD_DATA[10]}]
set_property PACKAGE_PIN U20 [get_ports {LCD_DATA[11]}]
set_property PACKAGE_PIN V20 [get_ports {LCD_DATA[12]}]
set_property PACKAGE_PIN W20 [get_ports {LCD_DATA[13]}]
set_property PACKAGE_PIN Y18 [get_ports {LCD_DATA[14]}]
set_property PACKAGE_PIN Y19 [get_ports {LCD_DATA[15]}]
set_property PACKAGE_PIN P18 [get_ports BP]
set_property PACKAGE_PIN P15 [get_ports iic_0_sda_io]
set_property PACKAGE_PIN P16 [get_ports iic_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports BP]
set_property IOSTANDARD LVCMOS33 [get_ports iic_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports iic_0_sda_io]
set_property PACKAGE_PIN N17 [get_ports MEMS_INTn]
set_property IOSTANDARD LVCMOS33 [get_ports MEMS_INTn]
set_property PACKAGE_PIN V16 [get_ports LCD_VSYNC]
set_property PACKAGE_PIN W16 [get_ports LCD_HSYNC]
set_property PACKAGE_PIN R16 [get_ports LCD_DE]
set_property PACKAGE_PIN R17 [get_ports LCD_PCLK]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_PCLK]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_HSYNC]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_DE]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_VSYNC]
set_property PACKAGE_PIN W18 [get_ports I2S_DIN]
set_property PACKAGE_PIN V18 [get_ports I2S_FSYNC_IN]
set_property IOSTANDARD LVCMOS33 [get_ports I2S_DIN]
set_property IOSTANDARD LVCMOS33 [get_ports I2S_FSYNC_IN]
set_property PACKAGE_PIN P14 [get_ports IO_B34_LP6]
set_property PACKAGE_PIN W14 [get_ports IO_B34_LP8]
set_property PACKAGE_PIN Y14 [get_ports IO_B34_LN8]
set_property PACKAGE_PIN U14 [get_ports IO_B34_LP11]
set_property PACKAGE_PIN U15 [get_ports IO_B34_LN11]
set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LP11]
set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LP8]
set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LN11]
set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LN8]
set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LP6]
set_property PACKAGE_PIN C20 [get_ports {IO_B35_LP[1]}]
set_property PACKAGE_PIN B20 [get_ports {IO_B35_LN[1]}]
set_property PACKAGE_PIN A20 [get_ports {IO_B35_LN[2]}]
set_property PACKAGE_PIN B19 [get_ports {IO_B35_LP[2]}]
set_property PACKAGE_PIN E17 [get_ports {IO_B35_LP[3]}]
set_property PACKAGE_PIN D18 [get_ports {IO_B35_LN[3]}]
set_property PACKAGE_PIN D19 [get_ports {IO_B35_LP[4]}]
set_property PACKAGE_PIN D20 [get_ports {IO_B35_LN[4]}]
set_property PACKAGE_PIN E18 [get_ports {IO_B35_LP[5]}]
set_property PACKAGE_PIN E19 [get_ports {IO_B35_LN[5]}]
set_property PACKAGE_PIN F16 [get_ports {IO_B35_LP[6]}]
set_property PACKAGE_PIN F17 [get_ports {IO_B35_LN[6]}]
set_property PACKAGE_PIN M19 [get_ports {IO_B35_LP[7]}]
set_property PACKAGE_PIN M20 [get_ports {IO_B35_LN[7]}]
set_property PACKAGE_PIN M17 [get_ports {IO_B35_LP[8]}]
set_property PACKAGE_PIN M18 [get_ports {IO_B35_LN[8]}]
set_property PACKAGE_PIN L19 [get_ports {IO_B35_LP[9]}]
set_property PACKAGE_PIN L20 [get_ports {IO_B35_LN[9]}]
set_property PACKAGE_PIN K19 [get_ports {IO_B35_LP[10]}]
set_property PACKAGE_PIN J19 [get_ports {IO_B35_LN[10]}]
set_property PACKAGE_PIN L16 [get_ports {IO_B35_LP[11]}]
set_property PACKAGE_PIN L17 [get_ports {IO_B35_LN[11]}]
set_property PACKAGE_PIN K17 [get_ports {IO_B35_LP[12]}]
set_property PACKAGE_PIN K18 [get_ports {IO_B35_LN[12]}]
set_property PACKAGE_PIN H16 [get_ports {IO_B35_LP[13]}]
set_property PACKAGE_PIN H17 [get_ports {IO_B35_LN[13]}]
set_property PACKAGE_PIN J18 [get_ports {IO_B35_LP[14]}]
set_property PACKAGE_PIN H18 [get_ports {IO_B35_LN[14]}]
set_property PACKAGE_PIN F19 [get_ports {IO_B35_LP[15]}]
set_property PACKAGE_PIN F20 [get_ports {IO_B35_LN[15]}]
set_property PACKAGE_PIN G17 [get_ports {IO_B35_LP[16]}]
set_property PACKAGE_PIN G18 [get_ports {IO_B35_LN[16]}]
set_property PACKAGE_PIN J20 [get_ports {IO_B35_LP[17]}]
set_property PACKAGE_PIN H20 [get_ports {IO_B35_LN[17]}]
set_property PACKAGE_PIN G19 [get_ports {IO_B35_LP[18]}]
set_property PACKAGE_PIN G20 [get_ports {IO_B35_LN[18]}]
set_property PACKAGE_PIN H15 [get_ports {IO_B35_LP[19]}]
set_property PACKAGE_PIN G15 [get_ports {IO_B35_LN[19]}]
set_property PACKAGE_PIN K14 [get_ports {IO_B35_LP[20]}]
set_property PACKAGE_PIN J14 [get_ports {IO_B35_LN[20]}]
set_property PACKAGE_PIN N15 [get_ports {IO_B35_LP[21]}]
set_property PACKAGE_PIN N16 [get_ports {IO_B35_LN[21]}]
set_property PACKAGE_PIN L14 [get_ports {IO_B35_LP[22]}]
set_property PACKAGE_PIN L15 [get_ports {IO_B35_LN[22]}]
set_property PACKAGE_PIN M14 [get_ports {IO_B35_LP[23]}]
set_property PACKAGE_PIN M15 [get_ports {IO_B35_LN[23]}]
set_property PACKAGE_PIN K16 [get_ports {IO_B35_LP[24]}]
set_property PACKAGE_PIN J16 [get_ports {IO_B35_LN[24]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports HDMI_INTn]
set_property PACKAGE_PIN W19 [get_ports HDMI_INTn]
set_property IOSTANDARD LVCMOS33 [get_ports I2S_FSYNC_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports I2S_SCLK]
set_property IOSTANDARD LVCMOS33 [get_ports I2S_DOUT]
set_property PACKAGE_PIN V17 [get_ports I2S_DOUT]
set_property PACKAGE_PIN T17 [get_ports I2S_SCLK]
set_property PACKAGE_PIN R18 [get_ports I2S_FSYNC_OUT]
set_property PACKAGE_PIN R19 [get_ports {SW[0]}]
set_property PACKAGE_PIN T19 [get_ports {SW[1]}]
set_property PACKAGE_PIN G14 [get_ports {SW[2]}]
set_property PACKAGE_PIN J15 [get_ports {SW[3]}]
set_property PACKAGE_PIN Y16 [get_ports {LEDS[0]}]
set_property PACKAGE_PIN Y17 [get_ports {LEDS[1]}]
set_property PACKAGE_PIN R14 [get_ports {LEDS[2]}]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

BIN
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.hwdef Normal file
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Binary file not shown.

2007
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.v Normal file
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224
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn_wrapper.v Normal file
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@ -0,0 +1,224 @@
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
//Date : Wed Jul 15 11:10:09 2015
//Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
//Command : generate_target z_turn_wrapper.bd
//Design : z_turn_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module z_turn_wrapper
(BP,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
HDMI_INTn,
I2S_DIN,
I2S_DOUT,
I2S_FSYNC_IN,
I2S_FSYNC_OUT,
I2S_SCLK,
IO_B34_LN,
IO_B34_LN11,
IO_B34_LN8,
IO_B34_LP,
IO_B34_LP11,
IO_B34_LP6,
IO_B34_LP8,
IO_B35_LN,
IO_B35_LP,
LCD_DATA,
LCD_DE,
LCD_HSYNC,
LCD_PCLK,
LCD_VSYNC,
LEDS,
MEMS_INTn,
SW,
iic_0_scl_io,
iic_0_sda_io);
output BP;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input HDMI_INTn;
input I2S_DIN;
output I2S_DOUT;
input I2S_FSYNC_IN;
output I2S_FSYNC_OUT;
output I2S_SCLK;
input [5:1]IO_B34_LN;
input IO_B34_LN11;
input IO_B34_LN8;
input [5:1]IO_B34_LP;
input IO_B34_LP11;
input IO_B34_LP6;
input IO_B34_LP8;
input [24:1]IO_B35_LN;
input [24:1]IO_B35_LP;
output [15:0]LCD_DATA;
output LCD_DE;
output LCD_HSYNC;
output LCD_PCLK;
output LCD_VSYNC;
output [2:0]LEDS;
input MEMS_INTn;
input [3:0]SW;
inout iic_0_scl_io;
inout iic_0_sda_io;
wire BP;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire HDMI_INTn;
wire I2S_DIN;
wire I2S_DOUT;
wire I2S_FSYNC_IN;
wire I2S_FSYNC_OUT;
wire I2S_SCLK;
wire [5:1]IO_B34_LN;
wire IO_B34_LN11;
wire IO_B34_LN8;
wire [5:1]IO_B34_LP;
wire IO_B34_LP11;
wire IO_B34_LP6;
wire IO_B34_LP8;
wire [24:1]IO_B35_LN;
wire [24:1]IO_B35_LP;
wire [15:0]LCD_DATA;
wire LCD_DE;
wire LCD_HSYNC;
wire LCD_PCLK;
wire LCD_VSYNC;
wire [2:0]LEDS;
wire MEMS_INTn;
wire [3:0]SW;
wire iic_0_scl_i;
wire iic_0_scl_io;
wire iic_0_scl_o;
wire iic_0_scl_t;
wire iic_0_sda_i;
wire iic_0_sda_io;
wire iic_0_sda_o;
wire iic_0_sda_t;
IOBUF iic_0_scl_iobuf
(.I(iic_0_scl_o),
.IO(iic_0_scl_io),
.O(iic_0_scl_i),
.T(iic_0_scl_t));
IOBUF iic_0_sda_iobuf
(.I(iic_0_sda_o),
.IO(iic_0_sda_io),
.O(iic_0_sda_i),
.T(iic_0_sda_t));
z_turn z_turn_i
(.BP(BP),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.HDMI_INTn(HDMI_INTn),
.I2S_DIN(I2S_DIN),
.I2S_DOUT(I2S_DOUT),
.I2S_FSYNC_IN(I2S_FSYNC_IN),
.I2S_FSYNC_OUT(I2S_FSYNC_OUT),
.I2S_SCLK(I2S_SCLK),
.IIC_0_scl_i(iic_0_scl_i),
.IIC_0_scl_o(iic_0_scl_o),
.IIC_0_scl_t(iic_0_scl_t),
.IIC_0_sda_i(iic_0_sda_i),
.IIC_0_sda_o(iic_0_sda_o),
.IIC_0_sda_t(iic_0_sda_t),
.IO_B34_LN(IO_B34_LN),
.IO_B34_LN11(IO_B34_LN11),
.IO_B34_LN8(IO_B34_LN8),
.IO_B34_LP(IO_B34_LP),
.IO_B34_LP11(IO_B34_LP11),
.IO_B34_LP6(IO_B34_LP6),
.IO_B34_LP8(IO_B34_LP8),
.IO_B35_LN(IO_B35_LN),
.IO_B35_LP(IO_B35_LP),
.LCD_DATA(LCD_DATA),
.LCD_DE(LCD_DE),
.LCD_HSYNC(LCD_HSYNC),
.LCD_PCLK(LCD_PCLK),
.LCD_VSYNC(LCD_VSYNC),
.LEDS(LEDS),
.MEMS_INTn(MEMS_INTn),
.SW(SW));
endmodule

3298
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hw_handoff/z_turn.hwh Normal file
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300
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hw_handoff/z_turn_bd.tcl Normal file
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################################################################
# This is a generated script based on design: z_turn
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2015.2
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source z_turn_script.tcl
# If you do not already have a project created,
# you can create a project using the following command:
# create_project project_1 myproj -part xc7z020clg400-1
# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
puts "ERROR: Please open or create a project!"
return 1
}
# CHANGE DESIGN NAME HERE
set design_name z_turn
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
puts "INFO: Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
puts "INFO: Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
puts $errMsg
return $nRet
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
set IIC_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_0 ]
# Create ports
set BP [ create_bd_port -dir O BP ]
set HDMI_INTn [ create_bd_port -dir I HDMI_INTn ]
set I2S_DIN [ create_bd_port -dir I I2S_DIN ]
set I2S_DOUT [ create_bd_port -dir O I2S_DOUT ]
set I2S_FSYNC_IN [ create_bd_port -dir I I2S_FSYNC_IN ]
set I2S_FSYNC_OUT [ create_bd_port -dir O I2S_FSYNC_OUT ]
set I2S_SCLK [ create_bd_port -dir O -type clk I2S_SCLK ]
set IO_B34_LN [ create_bd_port -dir I -from 5 -to 1 IO_B34_LN ]
set IO_B34_LN8 [ create_bd_port -dir I IO_B34_LN8 ]
set IO_B34_LN11 [ create_bd_port -dir I IO_B34_LN11 ]
set IO_B34_LP [ create_bd_port -dir I -from 5 -to 1 IO_B34_LP ]
set IO_B34_LP6 [ create_bd_port -dir I IO_B34_LP6 ]
set IO_B34_LP8 [ create_bd_port -dir I IO_B34_LP8 ]
set IO_B34_LP11 [ create_bd_port -dir I -type clk IO_B34_LP11 ]
set_property -dict [ list CONFIG.FREQ_HZ {50000000} ] $IO_B34_LP11
set IO_B35_LN [ create_bd_port -dir I -from 24 -to 1 -type data IO_B35_LN ]
set IO_B35_LP [ create_bd_port -dir I -from 24 -to 1 -type data IO_B35_LP ]
set LCD_DATA [ create_bd_port -dir O -from 15 -to 0 -type data LCD_DATA ]
set LCD_DE [ create_bd_port -dir O LCD_DE ]
set LCD_HSYNC [ create_bd_port -dir O LCD_HSYNC ]
set LCD_PCLK [ create_bd_port -dir O -type clk LCD_PCLK ]
set LCD_VSYNC [ create_bd_port -dir O LCD_VSYNC ]
set LEDS [ create_bd_port -dir O -from 2 -to 0 LEDS ]
set MEMS_INTn [ create_bd_port -dir I MEMS_INTn ]
set SW [ create_bd_port -dir I -from 3 -to 0 SW ]
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
# Create instance: proc_sys_reset_1, and set properties
set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]
# Create instance: proc_sys_reset_2, and set properties
set proc_sys_reset_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_2 ]
# Create instance: proc_sys_reset_3, and set properties
set proc_sys_reset_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_3 ]
# Create instance: ps7, and set properties
set ps7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 ps7 ]
set_property -dict [ list CONFIG.PCW_CAN0_CAN0_IO {MIO 14 .. 15} \
CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_ENET_RESET_ENABLE {0} CONFIG.PCW_EN_CLK1_PORT {1} \
CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} \
CONFIG.PCW_EN_RST1_PORT {1} CONFIG.PCW_EN_RST2_PORT {1} \
CONFIG.PCW_EN_RST3_PORT {1} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {166.667} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} CONFIG.PCW_I2C1_I2C1_IO {MIO 12 .. 13} \
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} CONFIG.PCW_I2C_RESET_ENABLE {0} \
CONFIG.PCW_IRQ_F2P_INTR {1} CONFIG.PCW_MIO_51_PULLUP {disabled} \
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SD0_GRP_CD_ENABLE {1} CONFIG.PCW_SD0_GRP_CD_IO {MIO 46} \
CONFIG.PCW_SD0_GRP_WP_ENABLE {1} CONFIG.PCW_SD0_GRP_WP_IO {MIO 47} \
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} CONFIG.PCW_UART0_UART0_IO {<Select>} \
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-15E} \
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} CONFIG.PCW_USB0_RESET_ENABLE {1} \
CONFIG.PCW_USB0_RESET_IO {MIO 51} CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
] $ps7
# Create instance: util_vector_logic_0, and set properties
set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
set_property -dict [ list CONFIG.C_OPERATION {not} CONFIG.C_SIZE {1} ] $util_vector_logic_0
# Create instance: util_vector_logic_1, and set properties
set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
set_property -dict [ list CONFIG.C_OPERATION {not} CONFIG.C_SIZE {1} ] $util_vector_logic_1
# Create instance: util_vector_logic_2, and set properties
set util_vector_logic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_2 ]
set_property -dict [ list CONFIG.C_OPERATION {not} CONFIG.C_SIZE {1} ] $util_vector_logic_2
# Create instance: xlconcat, and set properties
set xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat ]
set_property -dict [ list CONFIG.NUM_PORTS {16} ] $xlconcat
# Create instance: xlconcat_0, and set properties
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
set_property -dict [ list CONFIG.IN0_WIDTH {32} CONFIG.IN1_WIDTH {32} ] $xlconcat_0
# Create instance: xlconcat_1, and set properties
set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ]
set_property -dict [ list CONFIG.NUM_PORTS {32} ] $xlconcat_1
# Create instance: xlconcat_2, and set properties
set xlconcat_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_2 ]
set_property -dict [ list CONFIG.IN24_WIDTH {4} CONFIG.IN28_WIDTH {1} CONFIG.NUM_PORTS {29} ] $xlconcat_2
# Create instance: z_turn_ps_7_axi_periph_0, and set properties
set z_turn_ps_7_axi_periph_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 z_turn_ps_7_axi_periph_0 ]
set_property -dict [ list CONFIG.NUM_MI {1} CONFIG.S00_HAS_DATA_FIFO {0} ] $z_turn_ps_7_axi_periph_0
# Create instance: z_turn_ps_7_axi_periph_1, and set properties
set z_turn_ps_7_axi_periph_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 z_turn_ps_7_axi_periph_1 ]
set_property -dict [ list CONFIG.NUM_MI {1} CONFIG.S00_HAS_DATA_FIFO {0} ] $z_turn_ps_7_axi_periph_1
# Create interface connections
connect_bd_intf_net -intf_net io2axis_M00_AXI [get_bd_intf_pins ps7/S_AXI_HP0] [get_bd_intf_pins z_turn_ps_7_axi_periph_1/M00_AXI]
connect_bd_intf_net -intf_net ps7_IIC_0 [get_bd_intf_ports IIC_0] [get_bd_intf_pins ps7/IIC_0]
connect_bd_intf_net -intf_net ps_7_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins ps7/DDR]
connect_bd_intf_net -intf_net ps_7_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins ps7/FIXED_IO]
connect_bd_intf_net -intf_net ps_7_M_AXI_GP0 [get_bd_intf_pins ps7/M_AXI_GP0] [get_bd_intf_pins z_turn_ps_7_axi_periph_0/S00_AXI]
# Create port connections
connect_bd_net -net HDMI_INTn_1 [get_bd_ports HDMI_INTn] [get_bd_pins util_vector_logic_0/Op1]
connect_bd_net -net MEMS_INTn_1 [get_bd_ports MEMS_INTn] [get_bd_pins util_vector_logic_1/Op1] [get_bd_pins util_vector_logic_2/Op1]
connect_bd_net -net SW_1 [get_bd_ports SW] [get_bd_pins xlconcat_2/In24]
connect_bd_net -net proc_sys_reset2_interconnect_aresetn [get_bd_pins proc_sys_reset_2/interconnect_aresetn] [get_bd_pins z_turn_ps_7_axi_periph_1/ARESETN]
connect_bd_net -net proc_sys_reset2_peripheral_aresetn [get_bd_pins proc_sys_reset_2/peripheral_aresetn] [get_bd_pins z_turn_ps_7_axi_periph_1/M00_ARESETN] [get_bd_pins z_turn_ps_7_axi_periph_1/S00_ARESETN]
connect_bd_net -net ps_7_FCLK_CLK0 [get_bd_pins proc_sys_reset_1/slowest_sync_clk] [get_bd_pins ps7/FCLK_CLK1] [get_bd_pins ps7/M_AXI_GP0_ACLK] [get_bd_pins z_turn_ps_7_axi_periph_0/ACLK] [get_bd_pins z_turn_ps_7_axi_periph_0/M00_ACLK] [get_bd_pins z_turn_ps_7_axi_periph_0/S00_ACLK]
connect_bd_net -net ps_7_FCLK_CLK1 [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ps7/FCLK_CLK0]
connect_bd_net -net ps_7_FCLK_CLK2 [get_bd_pins proc_sys_reset_2/slowest_sync_clk] [get_bd_pins ps7/FCLK_CLK2] [get_bd_pins ps7/S_AXI_HP0_ACLK] [get_bd_pins z_turn_ps_7_axi_periph_1/ACLK] [get_bd_pins z_turn_ps_7_axi_periph_1/M00_ACLK] [get_bd_pins z_turn_ps_7_axi_periph_1/S00_ACLK]
connect_bd_net -net ps_7_FCLK_CLK3 [get_bd_pins proc_sys_reset_3/slowest_sync_clk] [get_bd_pins ps7/FCLK_CLK3]
connect_bd_net -net ps_7_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins ps7/FCLK_RESET0_N]
connect_bd_net -net ps_7_FCLK_RESET1_N [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins ps7/FCLK_RESET1_N]
connect_bd_net -net ps_7_FCLK_RESET2_N [get_bd_pins proc_sys_reset_2/ext_reset_in] [get_bd_pins ps7/FCLK_RESET2_N]
connect_bd_net -net ps_7_FCLK_RESET3_N [get_bd_pins proc_sys_reset_3/ext_reset_in] [get_bd_pins ps7/FCLK_RESET3_N]
connect_bd_net -net rst_ps_7_166M_interconnect_aresetn [get_bd_pins proc_sys_reset_1/interconnect_aresetn] [get_bd_pins z_turn_ps_7_axi_periph_0/ARESETN]
connect_bd_net -net rst_ps_7_166M_peripheral_aresetn [get_bd_pins proc_sys_reset_1/peripheral_aresetn] [get_bd_pins z_turn_ps_7_axi_periph_0/M00_ARESETN] [get_bd_pins z_turn_ps_7_axi_periph_0/S00_ARESETN]
connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] [get_bd_pins xlconcat/In0]
connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_1/Res] [get_bd_pins xlconcat/In2]
connect_bd_net -net util_vector_logic_2_Res [get_bd_pins util_vector_logic_2/Res] [get_bd_pins xlconcat/In3]
connect_bd_net -net xlconcat_0_dout [get_bd_pins ps7/IRQ_F2P] [get_bd_pins xlconcat/dout]
connect_bd_net -net xlconcat_0_dout1 [get_bd_pins ps7/GPIO_I] [get_bd_pins xlconcat_0/dout]
connect_bd_net -net xlconcat_1_dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlconcat_1/dout]
connect_bd_net -net xlconcat_2_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconcat_2/dout]
# Create address segments
# Restore current instance
current_bd_instance $oldCurInst
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/doc/proc_sys_reset_v5_0_changelog.txt Normal file
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2015.2:
* Version 5.0 (Rev. 7)
* No changes
2015.1:
* Version 5.0 (Rev. 7)
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 5.0 (Rev. 6)
* No changes
2014.4:
* Version 5.0 (Rev. 6)
* No changes
2014.3:
* Version 5.0 (Rev. 6)
* Modified to use new sub-cores in place of proc_common,no functional changes
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Updated core to use utils.tcl, needed for board flow from common location
2014.2:
* Version 5.0 (Rev. 5)
* Enhanced support for IP Integrator
* Board flow related updates, no functional changes
2014.1:
* Version 5.0 (Rev. 4)
* Internal device family name change, no functional changes
2013.4:
* Version 5.0 (Rev. 3)
* Added exdes.xdc file
* Changed the associated resets for slowest_sync_clk
* Kintex UltraScale Pre-Production support
2013.3:
* Version 5.0 (Rev. 2)
* Changed board flow specific parameter name as per new requirements
* Added example design and demonstration testbench
* Reduced warnings in synthesis and simulation
* Enhanced support for IP Integrator
* Added support for Cadence IES and Synopsys VCS simulators
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Support for 7-series devices at Production status
2013.2:
* Version 5.0 (Rev. 1)
* Added BETA support for future devices.
* No other RTL updates
2013.1:
* Version 5.0
* Updated version for 2013.1
* Updated bd.tcl for board flow
* No other RTL updates
(c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

138
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/sim/z_turn_proc_sys_reset1_0.vhd Normal file
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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY z_turn_proc_sys_reset1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_proc_sys_reset1_0;
ARCHITECTURE z_turn_proc_sys_reset1_0_arch OF z_turn_proc_sys_reset1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_proc_sys_reset1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END z_turn_proc_sys_reset1_0_arch;

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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY z_turn_proc_sys_reset1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_proc_sys_reset1_0;
ARCHITECTURE z_turn_proc_sys_reset1_0_arch OF z_turn_proc_sys_reset1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_proc_sys_reset1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF z_turn_proc_sys_reset1_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_proc_sys_reset1_0_arch : ARCHITECTURE IS "z_turn_proc_sys_reset1_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF z_turn_proc_sys_reset1_0_arch: ARCHITECTURE IS "z_turn_proc_sys_reset1_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END z_turn_proc_sys_reset1_0_arch;

16
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0.upgrade_log Normal file
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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:43:45 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_proc_sys_reset1_0'
1. Summary
----------
SUCCESS in the update of z_turn_proc_sys_reset1_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 7)) to current project options.

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0.veo Normal file
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// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
// IP Revision: 7
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
z_turn_proc_sys_reset1_0 your_instance_name (
.slowest_sync_clk(slowest_sync_clk), // input wire slowest_sync_clk
.ext_reset_in(ext_reset_in), // input wire ext_reset_in
.aux_reset_in(aux_reset_in), // input wire aux_reset_in
.mb_debug_sys_rst(mb_debug_sys_rst), // input wire mb_debug_sys_rst
.dcm_locked(dcm_locked), // input wire dcm_locked
.mb_reset(mb_reset), // output wire mb_reset
.bus_struct_reset(bus_struct_reset), // output wire [0 : 0] bus_struct_reset
.peripheral_reset(peripheral_reset), // output wire [0 : 0] peripheral_reset
.interconnect_aresetn(interconnect_aresetn), // output wire [0 : 0] interconnect_aresetn
.peripheral_aresetn(peripheral_aresetn) // output wire [0 : 0] peripheral_aresetn
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file z_turn_proc_sys_reset1_0.v when simulating
// the core, z_turn_proc_sys_reset1_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0.xci Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>z_turn_proc_sys_reset1_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">z_turn_proc_sys_reset1_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">z_turn_processing_system7_0_0_FCLK_CLK2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../ipshared</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

49
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0.xdc Normal file
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# file: z_turn_proc_sys_reset1_0.xdc
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set_false_path -to [get_pins -hier *cdc_to*/D]

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#--------------------Physical Constraints-----------------

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0_ooc.xdc Normal file
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# (c) Copyright 2012-2015 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk]
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports slowest_sync_clk]

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/doc/proc_sys_reset_v5_0_changelog.txt Normal file
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2015.2:
* Version 5.0 (Rev. 7)
* No changes
2015.1:
* Version 5.0 (Rev. 7)
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 5.0 (Rev. 6)
* No changes
2014.4:
* Version 5.0 (Rev. 6)
* No changes
2014.3:
* Version 5.0 (Rev. 6)
* Modified to use new sub-cores in place of proc_common,no functional changes
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Updated core to use utils.tcl, needed for board flow from common location
2014.2:
* Version 5.0 (Rev. 5)
* Enhanced support for IP Integrator
* Board flow related updates, no functional changes
2014.1:
* Version 5.0 (Rev. 4)
* Internal device family name change, no functional changes
2013.4:
* Version 5.0 (Rev. 3)
* Added exdes.xdc file
* Changed the associated resets for slowest_sync_clk
* Kintex UltraScale Pre-Production support
2013.3:
* Version 5.0 (Rev. 2)
* Changed board flow specific parameter name as per new requirements
* Added example design and demonstration testbench
* Reduced warnings in synthesis and simulation
* Enhanced support for IP Integrator
* Added support for Cadence IES and Synopsys VCS simulators
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Support for 7-series devices at Production status
2013.2:
* Version 5.0 (Rev. 1)
* Added BETA support for future devices.
* No other RTL updates
2013.1:
* Version 5.0
* Updated version for 2013.1
* Updated bd.tcl for board flow
* No other RTL updates
(c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/sim/z_turn_proc_sys_reset_1_0.vhd Normal file
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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY z_turn_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_proc_sys_reset_1_0;
ARCHITECTURE z_turn_proc_sys_reset_1_0_arch OF z_turn_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END z_turn_proc_sys_reset_1_0_arch;

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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY z_turn_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_proc_sys_reset_1_0;
ARCHITECTURE z_turn_proc_sys_reset_1_0_arch OF z_turn_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF z_turn_proc_sys_reset_1_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_proc_sys_reset_1_0_arch : ARCHITECTURE IS "z_turn_proc_sys_reset_1_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF z_turn_proc_sys_reset_1_0_arch: ARCHITECTURE IS "z_turn_proc_sys_reset_1_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END z_turn_proc_sys_reset_1_0_arch;

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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:43:46 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_proc_sys_reset_1_0'
1. Summary
----------
SUCCESS in the update of z_turn_proc_sys_reset_1_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 7)) to current project options.

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// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
// IP Revision: 7
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
z_turn_proc_sys_reset_1_0 your_instance_name (
.slowest_sync_clk(slowest_sync_clk), // input wire slowest_sync_clk
.ext_reset_in(ext_reset_in), // input wire ext_reset_in
.aux_reset_in(aux_reset_in), // input wire aux_reset_in
.mb_debug_sys_rst(mb_debug_sys_rst), // input wire mb_debug_sys_rst
.dcm_locked(dcm_locked), // input wire dcm_locked
.mb_reset(mb_reset), // output wire mb_reset
.bus_struct_reset(bus_struct_reset), // output wire [0 : 0] bus_struct_reset
.peripheral_reset(peripheral_reset), // output wire [0 : 0] peripheral_reset
.interconnect_aresetn(interconnect_aresetn), // output wire [0 : 0] interconnect_aresetn
.peripheral_aresetn(peripheral_aresetn) // output wire [0 : 0] peripheral_aresetn
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file z_turn_proc_sys_reset_1_0.v when simulating
// the core, z_turn_proc_sys_reset_1_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

66
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>z_turn_proc_sys_reset_1_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">z_turn_proc_sys_reset_1_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">200000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">z_turn_processing_system7_0_0_FCLK_CLK3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../ipshared</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/z_turn_proc_sys_reset_1_0.xdc Normal file
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# file: z_turn_proc_sys_reset_1_0.xdc
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set_false_path -to [get_pins -hier *cdc_to*/D]

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#--------------------Physical Constraints-----------------

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# (c) Copyright 2012-2015 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 5 -name slowest_sync_clk [get_ports slowest_sync_clk]
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports slowest_sync_clk]

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/doc/proc_sys_reset_v5_0_changelog.txt Normal file
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2015.2:
* Version 5.0 (Rev. 7)
* No changes
2015.1:
* Version 5.0 (Rev. 7)
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 5.0 (Rev. 6)
* No changes
2014.4:
* Version 5.0 (Rev. 6)
* No changes
2014.3:
* Version 5.0 (Rev. 6)
* Modified to use new sub-cores in place of proc_common,no functional changes
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Updated core to use utils.tcl, needed for board flow from common location
2014.2:
* Version 5.0 (Rev. 5)
* Enhanced support for IP Integrator
* Board flow related updates, no functional changes
2014.1:
* Version 5.0 (Rev. 4)
* Internal device family name change, no functional changes
2013.4:
* Version 5.0 (Rev. 3)
* Added exdes.xdc file
* Changed the associated resets for slowest_sync_clk
* Kintex UltraScale Pre-Production support
2013.3:
* Version 5.0 (Rev. 2)
* Changed board flow specific parameter name as per new requirements
* Added example design and demonstration testbench
* Reduced warnings in synthesis and simulation
* Enhanced support for IP Integrator
* Added support for Cadence IES and Synopsys VCS simulators
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Support for 7-series devices at Production status
2013.2:
* Version 5.0 (Rev. 1)
* Added BETA support for future devices.
* No other RTL updates
2013.1:
* Version 5.0
* Updated version for 2013.1
* Updated bd.tcl for board flow
* No other RTL updates
(c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/sim/z_turn_proc_sys_reset_3_0.vhd Normal file
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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY z_turn_proc_sys_reset_3_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_proc_sys_reset_3_0;
ARCHITECTURE z_turn_proc_sys_reset_3_0_arch OF z_turn_proc_sys_reset_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_proc_sys_reset_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END z_turn_proc_sys_reset_3_0_arch;

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/synth/z_turn_proc_sys_reset_3_0.vhd Normal file
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@ -0,0 +1,144 @@
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY z_turn_proc_sys_reset_3_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_proc_sys_reset_3_0;
ARCHITECTURE z_turn_proc_sys_reset_3_0_arch OF z_turn_proc_sys_reset_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_proc_sys_reset_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF z_turn_proc_sys_reset_3_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_proc_sys_reset_3_0_arch : ARCHITECTURE IS "z_turn_proc_sys_reset_3_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF z_turn_proc_sys_reset_3_0_arch: ARCHITECTURE IS "z_turn_proc_sys_reset_3_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END z_turn_proc_sys_reset_3_0_arch;

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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:43:47 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_proc_sys_reset_3_0'
1. Summary
----------
SUCCESS in the update of z_turn_proc_sys_reset_3_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 7)) to current project options.

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// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
// IP Revision: 7
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
z_turn_proc_sys_reset_3_0 your_instance_name (
.slowest_sync_clk(slowest_sync_clk), // input wire slowest_sync_clk
.ext_reset_in(ext_reset_in), // input wire ext_reset_in
.aux_reset_in(aux_reset_in), // input wire aux_reset_in
.mb_debug_sys_rst(mb_debug_sys_rst), // input wire mb_debug_sys_rst
.dcm_locked(dcm_locked), // input wire dcm_locked
.mb_reset(mb_reset), // output wire mb_reset
.bus_struct_reset(bus_struct_reset), // output wire [0 : 0] bus_struct_reset
.peripheral_reset(peripheral_reset), // output wire [0 : 0] peripheral_reset
.interconnect_aresetn(interconnect_aresetn), // output wire [0 : 0] interconnect_aresetn
.peripheral_aresetn(peripheral_aresetn) // output wire [0 : 0] peripheral_aresetn
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file z_turn_proc_sys_reset_3_0.v when simulating
// the core, z_turn_proc_sys_reset_3_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>z_turn_proc_sys_reset_3_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">z_turn_proc_sys_reset_3_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">166666672</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">z_turn_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../ipshared</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

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# file: z_turn_proc_sys_reset_3_0.xdc
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set_false_path -to [get_pins -hier *cdc_to*/D]

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#--------------------Physical Constraints-----------------

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# (c) Copyright 2012-2015 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 6 -name slowest_sync_clk [get_ports slowest_sync_clk]
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports slowest_sync_clk]

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/doc/processing_system7_v5_5_changelog.txt Normal file
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2015.2:
* Version 5.5 (Rev. 1)
* No changes
2015.1:
* Version 5.5 (Rev. 1)
* Added support and functionality for Secure and Non-Secure
* Removed wire ENET0_GMII_TX_EN_i
* Wire ENET0_GMII_TX_ER_i; and the signals were tied low
* Added functionality for TRACE_CTL_PIPE
* Secure/Non-Secure Access configuration Enablement added in General settings
* DDR training board details were updated with revised scale and correct values
* Writing to register tpiu Curentsize (0xF8803004) register is removed if trace is disabled
* Dynamic Trace Pipeline width configuration based on user choice
* Adding keep option for Trace Control & Data registers
* If JTAG OBUF is disabled; the PJTAG_TDO is set to ‘0’
2014.4.1:
* Version 5.5
* No changes
2014.4:
* Version 5.5
* No changes
2014.3:
* Version 5.5
* The custom time stamp unit(PTP) signals will be exposed to the Programmable Logic(PL), even when the Ethernet is routed through the MIO. For more details, please refer Zynq Technical Reference Manual (UG 585) CH No. 16.4 IEEE 1588 Time Stamping. This change enables additional optional functionality for designs with Ethernet on MIO. No changes are required for existing designs
* Updated Trace data port width dependency to be based on Trace parameters Port width will display based on user selection
* Updated the JTAG interface from master to slave mode. Based on Zynq Technical Reference Manual, PS boot mode supports 4 master boot mode and 2 Slave JTAG Boot mode. Prior versions of Zynq PS7 IP had PL JTAG in master mode incorrectly. The JTAG port TDO will have a buffer (OBUFT) instantiated as part of the Processing System7 IP. This change only affects designs which use PL JTAG through EMIO interface. For More details, refer chapter no.6 of Zynq Technical Reference Manual (UG 585) - Boot and Configuration
* Added range validation for SMC cycle parameters
* Prior versions of PS7 IP had writes to certain reserved bits of DDR IOB Buffer Control (DDRIOB_DDR_CTRL). These have been fixed to 0x0.
2014.2:
* Version 5.4 (Rev. 1)
* Add the polarity feature for reset (USB, I2C and Ethernet) pins
* Add the IP type is processor
* Fixed LPDDR2 hang Issue
2014.1:
* Version 5.4
* IRQ_F2P connections to be made directly in the silicon
2013.4:
* Version 5.3 (Rev. 1)
* DDRIOB_SLEW registers added in ps7_init
* Removed toggling of FPGA_RST_CTRL register from post_config
* Trace enabled for different port size such as 2,4,8,16 and 32 bits
2013.3:
* Version 5.3
* Added Microzed board preset In ps7 ip
* xz0303 SBG package added
* TCL based preset support for Zynq
* Zynq BFM subcore added for simulation support
2013.2:
* Version 5.2
* Zynq Power Estimation Support added
* Extended addresing support for SMC memories, QSPI memory, PS registers and SLCR registers
* Peripheral I/O pin page made more user interactive
2013.1:
* Version 5.01
* Added support for ps7 preset configurations
* Multiple silicon version support
* Ps7 gui enhanced to vivado standard
(c) Copyright 2002 - 2015 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

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//

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/******************************************************************************
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this
* software and associated documentation files (the "Software"), to deal in the Software
* without restriction, including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
* otherwise to promote the sale, use or other dealings in this Software without prior written
* authorization from Xilinx.
*
*******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158731
#define QSPI_FREQ 200000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 100000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 100000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 166666672
#define FPGA1_FREQ 50000000
#define FPGA2_FREQ 100000000
#define FPGA3_FREQ 200000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif

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proc ps7_pll_init_data_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00302301
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000501
mask_write 0XF8000150 0x00003F33 0x00000A01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF800015C 0x03F03F33 0x00100A01
mask_write 0XF8000160 0x007F007F 0x00000000
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00100600
mask_write 0XF8000180 0x03F03F30 0x00101400
mask_write 0XF8000190 0x03F03F30 0x00100A00
mask_write 0XF80001A0 0x03F03F30 0x00100500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01ED044D
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x0007FFFF 0x00001081
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004281B
mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
mask_write 0XF8006034 0x13FF3FFF 0x00011054
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000003
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00018000
mask_write 0XF8006130 0x000FFFFF 0x00018000
mask_write 0XF8006134 0x000FFFFF 0x00018000
mask_write 0XF8006138 0x000FFFFF 0x00018000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000B5
mask_write 0XF800616C 0x001FFFFF 0x000000B5
mask_write 0XF8006170 0x001FFFFF 0x000000B5
mask_write 0XF8006174 0x001FFFFF 0x000000B5
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x00001640
mask_write 0XF8000734 0x00003FFF 0x00001640
mask_write 0XF8000738 0x00003FFF 0x00001621
mask_write 0XF800073C 0x00003FFF 0x00001620
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF8000770 0x00003FFF 0x00001204
mask_write 0XF8000774 0x00003FFF 0x00001205
mask_write 0XF8000778 0x00003FFF 0x00001204
mask_write 0XF800077C 0x00003FFF 0x00001205
mask_write 0XF8000780 0x00003FFF 0x00001204
mask_write 0XF8000784 0x00003FFF 0x00001204
mask_write 0XF8000788 0x00003FFF 0x00001204
mask_write 0XF800078C 0x00003FFF 0x00001204
mask_write 0XF8000790 0x00003FFF 0x00001205
mask_write 0XF8000794 0x00003FFF 0x00001204
mask_write 0XF8000798 0x00003FFF 0x00001204
mask_write 0XF800079C 0x00003FFF 0x00001204
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007C8 0x00003FFF 0x00001200
mask_write 0XF80007CC 0x00003FFF 0x00000200
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002E002F
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mask_write 0XF8000004 0x0000FFFF 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
mask_write 0XE000A244 0x003FFFFF 0x00080000
mask_write 0XE000A00C 0x003F003F 0x00370008
mask_write 0XE000A248 0x003FFFFF 0x00080000
mask_write 0XE000A00C 0x003F003F 0x00370000
mask_delay 0XF8F00200 1
mask_write 0XE000A00C 0x003F003F 0x00370008
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
}
proc ps7_post_config_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_debug_3_0 {} {
mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55
mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55
mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00302301
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000501
mask_write 0XF8000150 0x00003F33 0x00000A01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF800015C 0x03F03F33 0x00100A01
mask_write 0XF8000160 0x007F007F 0x00000000
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00100600
mask_write 0XF8000180 0x03F03F30 0x00101400
mask_write 0XF8000190 0x03F03F30 0x00100A00
mask_write 0XF80001A0 0x03F03F30 0x00100500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01ED044D
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004281B
mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
mask_write 0XF8006034 0x13FF3FFF 0x00011054
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000003
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00018000
mask_write 0XF8006130 0x000FFFFF 0x00018000
mask_write 0XF8006134 0x000FFFFF 0x00018000
mask_write 0XF8006138 0x000FFFFF 0x00018000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000B5
mask_write 0XF800616C 0x001FFFFF 0x000000B5
mask_write 0XF8006170 0x001FFFFF 0x000000B5
mask_write 0XF8006174 0x001FFFFF 0x000000B5
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x00001640
mask_write 0XF8000734 0x00003FFF 0x00001640
mask_write 0XF8000738 0x00003FFF 0x00001621
mask_write 0XF800073C 0x00003FFF 0x00001620
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF8000770 0x00003FFF 0x00001204
mask_write 0XF8000774 0x00003FFF 0x00001205
mask_write 0XF8000778 0x00003FFF 0x00001204
mask_write 0XF800077C 0x00003FFF 0x00001205
mask_write 0XF8000780 0x00003FFF 0x00001204
mask_write 0XF8000784 0x00003FFF 0x00001204
mask_write 0XF8000788 0x00003FFF 0x00001204
mask_write 0XF800078C 0x00003FFF 0x00001204
mask_write 0XF8000790 0x00003FFF 0x00001205
mask_write 0XF8000794 0x00003FFF 0x00001204
mask_write 0XF8000798 0x00003FFF 0x00001204
mask_write 0XF800079C 0x00003FFF 0x00001204
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007C8 0x00003FFF 0x00001200
mask_write 0XF80007CC 0x00003FFF 0x00000200
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002E002F
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mask_write 0XF8000004 0x0000FFFF 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
mask_write 0XE000A244 0x003FFFFF 0x00080000
mask_write 0XE000A00C 0x003F003F 0x00370008
mask_write 0XE000A248 0x003FFFFF 0x00080000
mask_write 0XE000A00C 0x003F003F 0x00370000
mask_delay 0XF8F00200 1
mask_write 0XE000A00C 0x003F003F 0x00370008
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
}
proc ps7_post_config_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_debug_2_0 {} {
mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55
mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55
mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00302301
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000501
mask_write 0XF8000150 0x00003F33 0x00000A01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF800015C 0x03F03F33 0x00100A01
mask_write 0XF8000160 0x007F007F 0x00000000
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00100600
mask_write 0XF8000180 0x03F03F30 0x00101400
mask_write 0XF8000190 0x03F03F30 0x00100A00
mask_write 0XF80001A0 0x03F03F30 0x00100500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01ED044D
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004281B
mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
mask_write 0XF8006034 0x13FF3FFF 0x00011054
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000003
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00018000
mask_write 0XF8006130 0x000FFFFF 0x00018000
mask_write 0XF8006134 0x000FFFFF 0x00018000
mask_write 0XF8006138 0x000FFFFF 0x00018000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000B5
mask_write 0XF800616C 0x001FFFFF 0x000000B5
mask_write 0XF8006170 0x001FFFFF 0x000000B5
mask_write 0XF8006174 0x001FFFFF 0x000000B5
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x00001640
mask_write 0XF8000734 0x00003FFF 0x00001640
mask_write 0XF8000738 0x00003FFF 0x00001621
mask_write 0XF800073C 0x00003FFF 0x00001620
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF8000770 0x00003FFF 0x00001204
mask_write 0XF8000774 0x00003FFF 0x00001205
mask_write 0XF8000778 0x00003FFF 0x00001204
mask_write 0XF800077C 0x00003FFF 0x00001205
mask_write 0XF8000780 0x00003FFF 0x00001204
mask_write 0XF8000784 0x00003FFF 0x00001204
mask_write 0XF8000788 0x00003FFF 0x00001204
mask_write 0XF800078C 0x00003FFF 0x00001204
mask_write 0XF8000790 0x00003FFF 0x00001205
mask_write 0XF8000794 0x00003FFF 0x00001204
mask_write 0XF8000798 0x00003FFF 0x00001204
mask_write 0XF800079C 0x00003FFF 0x00001204
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007C8 0x00003FFF 0x00001200
mask_write 0XF80007CC 0x00003FFF 0x00000200
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002E002F
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mask_write 0XF8000004 0x0000FFFF 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
mask_write 0XE000A244 0x003FFFFF 0x00080000
mask_write 0XE000A00C 0x003F003F 0x00370008
mask_write 0XE000A248 0x003FFFFF 0x00080000
mask_write 0XE000A00C 0x003F003F 0x00370000
mask_delay 0XF8F00200 1
mask_write 0XE000A00C 0x003F003F 0x00370008
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
mask_delay 0XF8F00200 1
}
proc ps7_post_config_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_debug_1_0 {} {
mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55
mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55
mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}

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/******************************************************************************
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this
* software and associated documentation files (the "Software"), to deal in the Software
* without restriction, including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
* otherwise to promote the sale, use or other dealings in this Software without prior written
* authorization from Xilinx.
*
*******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158731
#define QSPI_FREQ 200000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 100000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 100000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 166666672
#define FPGA1_FREQ 50000000
#define FPGA2_FREQ 100000000
#define FPGA3_FREQ 200000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
<designInfo version="1.0" >
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
<PARAMETERS >
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666" />
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="MIO 14 .. 15" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="10" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="35" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="3" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="6" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="20" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="10" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="166.667" />
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="64" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="EMIO" />
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="EMIO" />
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="MIO 12 .. 13" />
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="2" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="2" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="2" />
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="2" />
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="2" />
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="2" />
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="2" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="2" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="2" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="2" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8" />
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 46" />
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="MIO 47" />
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45" />
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="10" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="" />
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="54.563" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="54.563" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="54.563" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="54.563" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="101.239" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="79.5025" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="60.536" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="71.7715" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="104.5365" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="70.676" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="59.1615" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="81.319" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-15E" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="45.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="36.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="49.5" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="MIO 51" />
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39" />
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin" />
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="1" />
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
</PARAMETERS>
<BUSINTERFACES >
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="1" />
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
</BUSINTERFACES>
<CLOCKOUTS >
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="166.666672" />
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="50.000000" />
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="100.000000" />
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="200.000000" />
</CLOCKOUTS>
</MODULE>
</designInfo>

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/sim/z_turn_processing_system7_0_0.v Normal file
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// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module z_turn_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_CLK1,
FCLK_CLK2,
FCLK_CLK3,
FCLK_RESET0_N,
FCLK_RESET1_N,
FCLK_RESET2_N,
FCLK_RESET3_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
input [63 : 0] GPIO_I;
output [63 : 0] GPIO_O;
output [63 : 0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1 : 0] S_AXI_HP0_BRESP;
output [1 : 0] S_AXI_HP0_RRESP;
output [5 : 0] S_AXI_HP0_BID;
output [5 : 0] S_AXI_HP0_RID;
output [63 : 0] S_AXI_HP0_RDATA;
output [7 : 0] S_AXI_HP0_RCOUNT;
output [7 : 0] S_AXI_HP0_WCOUNT;
output [2 : 0] S_AXI_HP0_RACOUNT;
output [5 : 0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1 : 0] S_AXI_HP0_ARBURST;
input [1 : 0] S_AXI_HP0_ARLOCK;
input [2 : 0] S_AXI_HP0_ARSIZE;
input [1 : 0] S_AXI_HP0_AWBURST;
input [1 : 0] S_AXI_HP0_AWLOCK;
input [2 : 0] S_AXI_HP0_AWSIZE;
input [2 : 0] S_AXI_HP0_ARPROT;
input [2 : 0] S_AXI_HP0_AWPROT;
input [31 : 0] S_AXI_HP0_ARADDR;
input [31 : 0] S_AXI_HP0_AWADDR;
input [3 : 0] S_AXI_HP0_ARCACHE;
input [3 : 0] S_AXI_HP0_ARLEN;
input [3 : 0] S_AXI_HP0_ARQOS;
input [3 : 0] S_AXI_HP0_AWCACHE;
input [3 : 0] S_AXI_HP0_AWLEN;
input [3 : 0] S_AXI_HP0_AWQOS;
input [5 : 0] S_AXI_HP0_ARID;
input [5 : 0] S_AXI_HP0_AWID;
input [5 : 0] S_AXI_HP0_WID;
input [63 : 0] S_AXI_HP0_WDATA;
input [7 : 0] S_AXI_HP0_WSTRB;
input [15 : 0] IRQ_F2P;
output FCLK_CLK0;
output FCLK_CLK1;
output FCLK_CLK2;
output FCLK_CLK3;
output FCLK_RESET0_N;
output FCLK_RESET1_N;
output FCLK_RESET2_N;
output FCLK_RESET3_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(166.666672),
.C_FCLK_CLK1_FREQ(50.0),
.C_FCLK_CLK2_FREQ(100.0),
.C_FCLK_CLK3_FREQ(200.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(FCLK_CLK2),
.FCLK_CLK3(FCLK_CLK3),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(FCLK_RESET1_N),
.FCLK_RESET2_N(FCLK_RESET2_N),
.FCLK_RESET3_N(FCLK_RESET3_N),
.IRQ_F2P(IRQ_F2P),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule

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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:44:12 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_processing_system7_0_0'
1. Summary
----------
SUCCESS in the update of z_turn_processing_system7_0_0 (xilinx.com:ip:processing_system7:5.5 (Rev. 1)) to current project options.
2. Upgrade messages
-------------------
WARNING: upgrade cannot add parameter PCW_TRACE_INTERNAL_WIDTH with default value 32 : a parameter called PCW_TRACE_INTERNAL_WIDTH already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_USE_AXI_NONSECURE with default value 0 : a parameter called PCW_USE_AXI_NONSECURE already exists in processing_system7_v5_5

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// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 1
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
z_turn_processing_system7_0_0 your_instance_name (
.ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX), // output wire ENET0_PTP_DELAY_REQ_RX
.ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX), // output wire ENET0_PTP_DELAY_REQ_TX
.ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX), // output wire ENET0_PTP_PDELAY_REQ_RX
.ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX), // output wire ENET0_PTP_PDELAY_REQ_TX
.ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX), // output wire ENET0_PTP_PDELAY_RESP_RX
.ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX), // output wire ENET0_PTP_PDELAY_RESP_TX
.ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX), // output wire ENET0_PTP_SYNC_FRAME_RX
.ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX), // output wire ENET0_PTP_SYNC_FRAME_TX
.ENET0_SOF_RX(ENET0_SOF_RX), // output wire ENET0_SOF_RX
.ENET0_SOF_TX(ENET0_SOF_TX), // output wire ENET0_SOF_TX
.GPIO_I(GPIO_I), // input wire [63 : 0] GPIO_I
.GPIO_O(GPIO_O), // output wire [63 : 0] GPIO_O
.GPIO_T(GPIO_T), // output wire [63 : 0] GPIO_T
.I2C0_SDA_I(I2C0_SDA_I), // input wire I2C0_SDA_I
.I2C0_SDA_O(I2C0_SDA_O), // output wire I2C0_SDA_O
.I2C0_SDA_T(I2C0_SDA_T), // output wire I2C0_SDA_T
.I2C0_SCL_I(I2C0_SCL_I), // input wire I2C0_SCL_I
.I2C0_SCL_O(I2C0_SCL_O), // output wire I2C0_SCL_O
.I2C0_SCL_T(I2C0_SCL_T), // output wire I2C0_SCL_T
.USB0_PORT_INDCTL(USB0_PORT_INDCTL), // output wire [1 : 0] USB0_PORT_INDCTL
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), // output wire USB0_VBUS_PWRSELECT
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), // input wire USB0_VBUS_PWRFAULT
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), // output wire M_AXI_GP0_ARVALID
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), // output wire M_AXI_GP0_AWVALID
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), // output wire M_AXI_GP0_BREADY
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), // output wire M_AXI_GP0_RREADY
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), // output wire M_AXI_GP0_WLAST
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), // output wire M_AXI_GP0_WVALID
.M_AXI_GP0_ARID(M_AXI_GP0_ARID), // output wire [11 : 0] M_AXI_GP0_ARID
.M_AXI_GP0_AWID(M_AXI_GP0_AWID), // output wire [11 : 0] M_AXI_GP0_AWID
.M_AXI_GP0_WID(M_AXI_GP0_WID), // output wire [11 : 0] M_AXI_GP0_WID
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), // output wire [1 : 0] M_AXI_GP0_ARBURST
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), // output wire [1 : 0] M_AXI_GP0_ARLOCK
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), // output wire [2 : 0] M_AXI_GP0_ARSIZE
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), // output wire [1 : 0] M_AXI_GP0_AWBURST
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), // output wire [1 : 0] M_AXI_GP0_AWLOCK
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), // output wire [2 : 0] M_AXI_GP0_AWSIZE
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), // output wire [2 : 0] M_AXI_GP0_ARPROT
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), // output wire [2 : 0] M_AXI_GP0_AWPROT
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), // output wire [31 : 0] M_AXI_GP0_ARADDR
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), // output wire [31 : 0] M_AXI_GP0_AWADDR
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), // output wire [31 : 0] M_AXI_GP0_WDATA
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), // output wire [3 : 0] M_AXI_GP0_ARCACHE
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), // output wire [3 : 0] M_AXI_GP0_ARLEN
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), // output wire [3 : 0] M_AXI_GP0_ARQOS
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), // output wire [3 : 0] M_AXI_GP0_AWCACHE
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), // output wire [3 : 0] M_AXI_GP0_AWLEN
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), // output wire [3 : 0] M_AXI_GP0_AWQOS
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), // output wire [3 : 0] M_AXI_GP0_WSTRB
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), // input wire M_AXI_GP0_ACLK
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), // input wire M_AXI_GP0_ARREADY
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), // input wire M_AXI_GP0_AWREADY
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), // input wire M_AXI_GP0_BVALID
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), // input wire M_AXI_GP0_RLAST
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), // input wire M_AXI_GP0_RVALID
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), // input wire M_AXI_GP0_WREADY
.M_AXI_GP0_BID(M_AXI_GP0_BID), // input wire [11 : 0] M_AXI_GP0_BID
.M_AXI_GP0_RID(M_AXI_GP0_RID), // input wire [11 : 0] M_AXI_GP0_RID
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), // input wire [1 : 0] M_AXI_GP0_BRESP
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), // input wire [1 : 0] M_AXI_GP0_RRESP
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), // input wire [31 : 0] M_AXI_GP0_RDATA
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY), // output wire S_AXI_HP0_ARREADY
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY), // output wire S_AXI_HP0_AWREADY
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID), // output wire S_AXI_HP0_BVALID
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST), // output wire S_AXI_HP0_RLAST
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID), // output wire S_AXI_HP0_RVALID
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY), // output wire S_AXI_HP0_WREADY
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP), // output wire [1 : 0] S_AXI_HP0_BRESP
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP), // output wire [1 : 0] S_AXI_HP0_RRESP
.S_AXI_HP0_BID(S_AXI_HP0_BID), // output wire [5 : 0] S_AXI_HP0_BID
.S_AXI_HP0_RID(S_AXI_HP0_RID), // output wire [5 : 0] S_AXI_HP0_RID
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA), // output wire [63 : 0] S_AXI_HP0_RDATA
.S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT), // output wire [7 : 0] S_AXI_HP0_RCOUNT
.S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT), // output wire [7 : 0] S_AXI_HP0_WCOUNT
.S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT), // output wire [2 : 0] S_AXI_HP0_RACOUNT
.S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT), // output wire [5 : 0] S_AXI_HP0_WACOUNT
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK), // input wire S_AXI_HP0_ACLK
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID), // input wire S_AXI_HP0_ARVALID
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID), // input wire S_AXI_HP0_AWVALID
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY), // input wire S_AXI_HP0_BREADY
.S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN), // input wire S_AXI_HP0_RDISSUECAP1_EN
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY), // input wire S_AXI_HP0_RREADY
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST), // input wire S_AXI_HP0_WLAST
.S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN), // input wire S_AXI_HP0_WRISSUECAP1_EN
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID), // input wire S_AXI_HP0_WVALID
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST), // input wire [1 : 0] S_AXI_HP0_ARBURST
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK), // input wire [1 : 0] S_AXI_HP0_ARLOCK
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE), // input wire [2 : 0] S_AXI_HP0_ARSIZE
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST), // input wire [1 : 0] S_AXI_HP0_AWBURST
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK), // input wire [1 : 0] S_AXI_HP0_AWLOCK
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE), // input wire [2 : 0] S_AXI_HP0_AWSIZE
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT), // input wire [2 : 0] S_AXI_HP0_ARPROT
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT), // input wire [2 : 0] S_AXI_HP0_AWPROT
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR), // input wire [31 : 0] S_AXI_HP0_ARADDR
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR), // input wire [31 : 0] S_AXI_HP0_AWADDR
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE), // input wire [3 : 0] S_AXI_HP0_ARCACHE
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN), // input wire [3 : 0] S_AXI_HP0_ARLEN
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS), // input wire [3 : 0] S_AXI_HP0_ARQOS
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE), // input wire [3 : 0] S_AXI_HP0_AWCACHE
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN), // input wire [3 : 0] S_AXI_HP0_AWLEN
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS), // input wire [3 : 0] S_AXI_HP0_AWQOS
.S_AXI_HP0_ARID(S_AXI_HP0_ARID), // input wire [5 : 0] S_AXI_HP0_ARID
.S_AXI_HP0_AWID(S_AXI_HP0_AWID), // input wire [5 : 0] S_AXI_HP0_AWID
.S_AXI_HP0_WID(S_AXI_HP0_WID), // input wire [5 : 0] S_AXI_HP0_WID
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA), // input wire [63 : 0] S_AXI_HP0_WDATA
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB), // input wire [7 : 0] S_AXI_HP0_WSTRB
.IRQ_F2P(IRQ_F2P), // input wire [15 : 0] IRQ_F2P
.FCLK_CLK0(FCLK_CLK0), // output wire FCLK_CLK0
.FCLK_CLK1(FCLK_CLK1), // output wire FCLK_CLK1
.FCLK_CLK2(FCLK_CLK2), // output wire FCLK_CLK2
.FCLK_CLK3(FCLK_CLK3), // output wire FCLK_CLK3
.FCLK_RESET0_N(FCLK_RESET0_N), // output wire FCLK_RESET0_N
.FCLK_RESET1_N(FCLK_RESET1_N), // output wire FCLK_RESET1_N
.FCLK_RESET2_N(FCLK_RESET2_N), // output wire FCLK_RESET2_N
.FCLK_RESET3_N(FCLK_RESET3_N), // output wire FCLK_RESET3_N
.MIO(MIO), // inout wire [53 : 0] MIO
.DDR_CAS_n(DDR_CAS_n), // inout wire DDR_CAS_n
.DDR_CKE(DDR_CKE), // inout wire DDR_CKE
.DDR_Clk_n(DDR_Clk_n), // inout wire DDR_Clk_n
.DDR_Clk(DDR_Clk), // inout wire DDR_Clk
.DDR_CS_n(DDR_CS_n), // inout wire DDR_CS_n
.DDR_DRSTB(DDR_DRSTB), // inout wire DDR_DRSTB
.DDR_ODT(DDR_ODT), // inout wire DDR_ODT
.DDR_RAS_n(DDR_RAS_n), // inout wire DDR_RAS_n
.DDR_WEB(DDR_WEB), // inout wire DDR_WEB
.DDR_BankAddr(DDR_BankAddr), // inout wire [2 : 0] DDR_BankAddr
.DDR_Addr(DDR_Addr), // inout wire [14 : 0] DDR_Addr
.DDR_VRN(DDR_VRN), // inout wire DDR_VRN
.DDR_VRP(DDR_VRP), // inout wire DDR_VRP
.DDR_DM(DDR_DM), // inout wire [3 : 0] DDR_DM
.DDR_DQ(DDR_DQ), // inout wire [31 : 0] DDR_DQ
.DDR_DQS_n(DDR_DQS_n), // inout wire [3 : 0] DDR_DQS_n
.DDR_DQS(DDR_DQS), // inout wire [3 : 0] DDR_DQS
.PS_SRSTB(PS_SRSTB), // inout wire PS_SRSTB
.PS_CLK(PS_CLK), // inout wire PS_CLK
.PS_PORB(PS_PORB) // inout wire PS_PORB
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file z_turn_processing_system7_0_0.v when simulating
// the core, z_turn_processing_system7_0_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

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############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
############################################################################
## File name : ps7_constraints.xdc
##
## Details : Constraints file
## FPGA family: zynq
## FPGA: xc7z020clg400-1
## Device Size: xc7z020
## Package: clg400
## Speedgrade: -1
##
##
############################################################################
############################################################################
############################################################################
# Clock constraints #
############################################################################
create_clock -name clk_fpga_2 -period "10" [get_pins "PS7_i/FCLKCLK[2]"]
set_input_jitter clk_fpga_2 0.3
#The clocks are asynchronous, user should constrain them appropriately.#
create_clock -name clk_fpga_0 -period "6" [get_pins "PS7_i/FCLKCLK[0]"]
set_input_jitter clk_fpga_0 0.18
#The clocks are asynchronous, user should constrain them appropriately.#
create_clock -name clk_fpga_1 -period "20" [get_pins "PS7_i/FCLKCLK[1]"]
set_input_jitter clk_fpga_1 0.6
#The clocks are asynchronous, user should constrain them appropriately.#
create_clock -name clk_fpga_3 -period "5" [get_pins "PS7_i/FCLKCLK[3]"]
set_input_jitter clk_fpga_3 0.15
#The clocks are asynchronous, user should constrain them appropriately.#
############################################################################
# I/O STANDARDS and Location Constraints #
############################################################################
# Enet 0 / mdio / MIO[53]
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
set_property slew "slow" [get_ports "MIO[53]"]
set_property drive "8" [get_ports "MIO[53]"]
set_property pullup "TRUE" [get_ports "MIO[53]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
# Enet 0 / mdc / MIO[52]
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
set_property slew "slow" [get_ports "MIO[52]"]
set_property drive "8" [get_ports "MIO[52]"]
set_property pullup "TRUE" [get_ports "MIO[52]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
# USB Reset / reset / MIO[51]
set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
set_property slew "slow" [get_ports "MIO[51]"]
set_property drive "8" [get_ports "MIO[51]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[51]"]
# GPIO / gpio[50] / MIO[50]
set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
set_property slew "slow" [get_ports "MIO[50]"]
set_property drive "8" [get_ports "MIO[50]"]
set_property pullup "TRUE" [get_ports "MIO[50]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
# UART 1 / rx / MIO[49]
set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
set_property slew "slow" [get_ports "MIO[49]"]
set_property drive "8" [get_ports "MIO[49]"]
set_property pullup "TRUE" [get_ports "MIO[49]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
# UART 1 / tx / MIO[48]
set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
set_property slew "slow" [get_ports "MIO[48]"]
set_property drive "8" [get_ports "MIO[48]"]
set_property pullup "TRUE" [get_ports "MIO[48]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
# SD 0 / wp / MIO[47]
set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
set_property slew "slow" [get_ports "MIO[47]"]
set_property drive "8" [get_ports "MIO[47]"]
set_property pullup "TRUE" [get_ports "MIO[47]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
# SD 0 / cd / MIO[46]
set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
set_property slew "slow" [get_ports "MIO[46]"]
set_property drive "8" [get_ports "MIO[46]"]
set_property pullup "TRUE" [get_ports "MIO[46]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[46]"]
# SD 0 / data[3] / MIO[45]
set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
set_property slew "slow" [get_ports "MIO[45]"]
set_property drive "8" [get_ports "MIO[45]"]
set_property pullup "TRUE" [get_ports "MIO[45]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
# SD 0 / data[2] / MIO[44]
set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
set_property slew "slow" [get_ports "MIO[44]"]
set_property drive "8" [get_ports "MIO[44]"]
set_property pullup "TRUE" [get_ports "MIO[44]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
# SD 0 / data[1] / MIO[43]
set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
set_property slew "slow" [get_ports "MIO[43]"]
set_property drive "8" [get_ports "MIO[43]"]
set_property pullup "TRUE" [get_ports "MIO[43]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
# SD 0 / data[0] / MIO[42]
set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
set_property slew "slow" [get_ports "MIO[42]"]
set_property drive "8" [get_ports "MIO[42]"]
set_property pullup "TRUE" [get_ports "MIO[42]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
# SD 0 / cmd / MIO[41]
set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
set_property slew "slow" [get_ports "MIO[41]"]
set_property drive "8" [get_ports "MIO[41]"]
set_property pullup "TRUE" [get_ports "MIO[41]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
# SD 0 / clk / MIO[40]
set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
set_property slew "slow" [get_ports "MIO[40]"]
set_property drive "8" [get_ports "MIO[40]"]
set_property pullup "TRUE" [get_ports "MIO[40]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
# USB 0 / data[7] / MIO[39]
set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
set_property slew "slow" [get_ports "MIO[39]"]
set_property drive "8" [get_ports "MIO[39]"]
set_property pullup "TRUE" [get_ports "MIO[39]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
# USB 0 / data[6] / MIO[38]
set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
set_property slew "slow" [get_ports "MIO[38]"]
set_property drive "8" [get_ports "MIO[38]"]
set_property pullup "TRUE" [get_ports "MIO[38]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
# USB 0 / data[5] / MIO[37]
set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
set_property slew "slow" [get_ports "MIO[37]"]
set_property drive "8" [get_ports "MIO[37]"]
set_property pullup "TRUE" [get_ports "MIO[37]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
# USB 0 / clk / MIO[36]
set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
set_property slew "slow" [get_ports "MIO[36]"]
set_property drive "8" [get_ports "MIO[36]"]
set_property pullup "TRUE" [get_ports "MIO[36]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
# USB 0 / data[3] / MIO[35]
set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
set_property slew "slow" [get_ports "MIO[35]"]
set_property drive "8" [get_ports "MIO[35]"]
set_property pullup "TRUE" [get_ports "MIO[35]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
# USB 0 / data[2] / MIO[34]
set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
set_property slew "slow" [get_ports "MIO[34]"]
set_property drive "8" [get_ports "MIO[34]"]
set_property pullup "TRUE" [get_ports "MIO[34]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
# USB 0 / data[1] / MIO[33]
set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
set_property slew "slow" [get_ports "MIO[33]"]
set_property drive "8" [get_ports "MIO[33]"]
set_property pullup "TRUE" [get_ports "MIO[33]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
# USB 0 / data[0] / MIO[32]
set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
set_property slew "slow" [get_ports "MIO[32]"]
set_property drive "8" [get_ports "MIO[32]"]
set_property pullup "TRUE" [get_ports "MIO[32]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
# USB 0 / nxt / MIO[31]
set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
set_property slew "slow" [get_ports "MIO[31]"]
set_property drive "8" [get_ports "MIO[31]"]
set_property pullup "TRUE" [get_ports "MIO[31]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
# USB 0 / stp / MIO[30]
set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
set_property slew "slow" [get_ports "MIO[30]"]
set_property drive "8" [get_ports "MIO[30]"]
set_property pullup "TRUE" [get_ports "MIO[30]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
# USB 0 / dir / MIO[29]
set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
set_property slew "slow" [get_ports "MIO[29]"]
set_property drive "8" [get_ports "MIO[29]"]
set_property pullup "TRUE" [get_ports "MIO[29]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
# USB 0 / data[4] / MIO[28]
set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
set_property slew "slow" [get_ports "MIO[28]"]
set_property drive "8" [get_ports "MIO[28]"]
set_property pullup "TRUE" [get_ports "MIO[28]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
# Enet 0 / rx_ctl / MIO[27]
set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
set_property slew "slow" [get_ports "MIO[27]"]
set_property drive "8" [get_ports "MIO[27]"]
set_property pullup "TRUE" [get_ports "MIO[27]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
# Enet 0 / rxd[3] / MIO[26]
set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
set_property slew "slow" [get_ports "MIO[26]"]
set_property drive "8" [get_ports "MIO[26]"]
set_property pullup "TRUE" [get_ports "MIO[26]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
# Enet 0 / rxd[2] / MIO[25]
set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
set_property slew "slow" [get_ports "MIO[25]"]
set_property drive "8" [get_ports "MIO[25]"]
set_property pullup "TRUE" [get_ports "MIO[25]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
# Enet 0 / rxd[1] / MIO[24]
set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
set_property slew "slow" [get_ports "MIO[24]"]
set_property drive "8" [get_ports "MIO[24]"]
set_property pullup "TRUE" [get_ports "MIO[24]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
# Enet 0 / rxd[0] / MIO[23]
set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
set_property slew "slow" [get_ports "MIO[23]"]
set_property drive "8" [get_ports "MIO[23]"]
set_property pullup "TRUE" [get_ports "MIO[23]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
# Enet 0 / rx_clk / MIO[22]
set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
set_property slew "slow" [get_ports "MIO[22]"]
set_property drive "8" [get_ports "MIO[22]"]
set_property pullup "TRUE" [get_ports "MIO[22]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
# Enet 0 / tx_ctl / MIO[21]
set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
set_property slew "slow" [get_ports "MIO[21]"]
set_property drive "8" [get_ports "MIO[21]"]
set_property pullup "TRUE" [get_ports "MIO[21]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
# Enet 0 / txd[3] / MIO[20]
set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
set_property slew "slow" [get_ports "MIO[20]"]
set_property drive "8" [get_ports "MIO[20]"]
set_property pullup "TRUE" [get_ports "MIO[20]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
# Enet 0 / txd[2] / MIO[19]
set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
set_property slew "slow" [get_ports "MIO[19]"]
set_property drive "8" [get_ports "MIO[19]"]
set_property pullup "TRUE" [get_ports "MIO[19]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
# Enet 0 / txd[1] / MIO[18]
set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
set_property slew "slow" [get_ports "MIO[18]"]
set_property drive "8" [get_ports "MIO[18]"]
set_property pullup "TRUE" [get_ports "MIO[18]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
# Enet 0 / txd[0] / MIO[17]
set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
set_property slew "slow" [get_ports "MIO[17]"]
set_property drive "8" [get_ports "MIO[17]"]
set_property pullup "TRUE" [get_ports "MIO[17]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
# Enet 0 / tx_clk / MIO[16]
set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
set_property slew "slow" [get_ports "MIO[16]"]
set_property drive "8" [get_ports "MIO[16]"]
set_property pullup "TRUE" [get_ports "MIO[16]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
# CAN 0 / tx / MIO[15]
set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
set_property slew "slow" [get_ports "MIO[15]"]
set_property drive "8" [get_ports "MIO[15]"]
set_property pullup "TRUE" [get_ports "MIO[15]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[15]"]
# CAN 0 / rx / MIO[14]
set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
set_property slew "slow" [get_ports "MIO[14]"]
set_property drive "8" [get_ports "MIO[14]"]
set_property pullup "TRUE" [get_ports "MIO[14]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[14]"]
# I2C 1 / sda / MIO[13]
set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
set_property slew "slow" [get_ports "MIO[13]"]
set_property drive "8" [get_ports "MIO[13]"]
set_property pullup "TRUE" [get_ports "MIO[13]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
# I2C 1 / scl / MIO[12]
set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
set_property slew "slow" [get_ports "MIO[12]"]
set_property drive "8" [get_ports "MIO[12]"]
set_property pullup "TRUE" [get_ports "MIO[12]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
# GPIO / gpio[11] / MIO[11]
set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
set_property slew "slow" [get_ports "MIO[11]"]
set_property drive "8" [get_ports "MIO[11]"]
set_property pullup "TRUE" [get_ports "MIO[11]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
# GPIO / gpio[10] / MIO[10]
set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
set_property slew "slow" [get_ports "MIO[10]"]
set_property drive "8" [get_ports "MIO[10]"]
set_property pullup "TRUE" [get_ports "MIO[10]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
# GPIO / gpio[9] / MIO[9]
set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
set_property slew "slow" [get_ports "MIO[9]"]
set_property drive "8" [get_ports "MIO[9]"]
set_property pullup "TRUE" [get_ports "MIO[9]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
# Quad SPI Flash / qspi_fbclk / MIO[8]
set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
set_property slew "slow" [get_ports "MIO[8]"]
set_property drive "8" [get_ports "MIO[8]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
# GPIO / gpio[7] / MIO[7]
set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
set_property slew "slow" [get_ports "MIO[7]"]
set_property drive "8" [get_ports "MIO[7]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
# Quad SPI Flash / qspi0_sclk / MIO[6]
set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
set_property slew "slow" [get_ports "MIO[6]"]
set_property drive "8" [get_ports "MIO[6]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
# Quad SPI Flash / qspi0_io[3] / MIO[5]
set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
set_property slew "slow" [get_ports "MIO[5]"]
set_property drive "8" [get_ports "MIO[5]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
# Quad SPI Flash / qspi0_io[2] / MIO[4]
set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
set_property slew "slow" [get_ports "MIO[4]"]
set_property drive "8" [get_ports "MIO[4]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
# Quad SPI Flash / qspi0_io[1] / MIO[3]
set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
set_property slew "slow" [get_ports "MIO[3]"]
set_property drive "8" [get_ports "MIO[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
# Quad SPI Flash / qspi0_io[0] / MIO[2]
set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
set_property slew "slow" [get_ports "MIO[2]"]
set_property drive "8" [get_ports "MIO[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
# Quad SPI Flash / qspi0_ss_b / MIO[1]
set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
set_property slew "slow" [get_ports "MIO[1]"]
set_property drive "8" [get_ports "MIO[1]"]
set_property pullup "TRUE" [get_ports "MIO[1]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
# GPIO / gpio[0] / MIO[0]
set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
set_property slew "slow" [get_ports "MIO[0]"]
set_property drive "8" [get_ports "MIO[0]"]
set_property pullup "TRUE" [get_ports "MIO[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
set_property slew "FAST" [get_ports "DDR_VRP"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
set_property slew "FAST" [get_ports "DDR_VRN"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
set_property slew "SLOW" [get_ports "DDR_WEB"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
set_property slew "SLOW" [get_ports "DDR_RAS_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
set_property slew "SLOW" [get_ports "DDR_ODT"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
set_property slew "FAST" [get_ports "DDR_DRSTB"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
set_property slew "FAST" [get_ports "DDR_DM[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
set_property slew "FAST" [get_ports "DDR_DM[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
set_property slew "FAST" [get_ports "DDR_DM[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
set_property slew "FAST" [get_ports "DDR_DM[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
set_property slew "SLOW" [get_ports "DDR_CS_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
set_property slew "SLOW" [get_ports "DDR_CKE"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
set_property slew "FAST" [get_ports "DDR_Clk"]
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
set_property slew "FAST" [get_ports "DDR_Clk_n"]
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
set_property slew "SLOW" [get_ports "DDR_CAS_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
set_property slew "slow" [get_ports "PS_PORB"]
set_property drive "8" [get_ports "PS_PORB"]
set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
set_property slew "slow" [get_ports "PS_SRSTB"]
set_property drive "8" [get_ports "PS_SRSTB"]
set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
set_property slew "slow" [get_ports "PS_CLK"]
set_property drive "8" [get_ports "PS_CLK"]

48500
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xml Normal file
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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.upgrade_log Normal file
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@ -0,0 +1,16 @@
Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:44:15 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_ps_7_axi_periph_0'
1. Summary
----------
SUCCESS in the update of z_turn_ps_7_axi_periph_0 (xilinx.com:ip:axi_interconnect:2.1 (Rev. 6)) to current project options.

341
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.xci Normal file
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@ -0,0 +1,341 @@
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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:44:16 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_ps_7_axi_periph_1'
1. Summary
----------
SUCCESS in the update of z_turn_ps_7_axi_periph_1 (xilinx.com:ip:axi_interconnect:2.1 (Rev. 6)) to current project options.

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.xml Normal file
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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/doc/proc_sys_reset_v5_0_changelog.txt Normal file
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@ -0,0 +1,104 @@
2015.2:
* Version 5.0 (Rev. 7)
* No changes
2015.1:
* Version 5.0 (Rev. 7)
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 5.0 (Rev. 6)
* No changes
2014.4:
* Version 5.0 (Rev. 6)
* No changes
2014.3:
* Version 5.0 (Rev. 6)
* Modified to use new sub-cores in place of proc_common,no functional changes
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Updated core to use utils.tcl, needed for board flow from common location
2014.2:
* Version 5.0 (Rev. 5)
* Enhanced support for IP Integrator
* Board flow related updates, no functional changes
2014.1:
* Version 5.0 (Rev. 4)
* Internal device family name change, no functional changes
2013.4:
* Version 5.0 (Rev. 3)
* Added exdes.xdc file
* Changed the associated resets for slowest_sync_clk
* Kintex UltraScale Pre-Production support
2013.3:
* Version 5.0 (Rev. 2)
* Changed board flow specific parameter name as per new requirements
* Added example design and demonstration testbench
* Reduced warnings in synthesis and simulation
* Enhanced support for IP Integrator
* Added support for Cadence IES and Synopsys VCS simulators
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Support for 7-series devices at Production status
2013.2:
* Version 5.0 (Rev. 1)
* Added BETA support for future devices.
* No other RTL updates
2013.1:
* Version 5.0
* Updated version for 2013.1
* Updated bd.tcl for board flow
* No other RTL updates
(c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY z_turn_rst_ps_7_166M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_rst_ps_7_166M_0;
ARCHITECTURE z_turn_rst_ps_7_166M_0_arch OF z_turn_rst_ps_7_166M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_rst_ps_7_166M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END z_turn_rst_ps_7_166M_0_arch;

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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY z_turn_rst_ps_7_166M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_rst_ps_7_166M_0;
ARCHITECTURE z_turn_rst_ps_7_166M_0_arch OF z_turn_rst_ps_7_166M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_rst_ps_7_166M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF z_turn_rst_ps_7_166M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_rst_ps_7_166M_0_arch : ARCHITECTURE IS "z_turn_rst_ps_7_166M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF z_turn_rst_ps_7_166M_0_arch: ARCHITECTURE IS "z_turn_rst_ps_7_166M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END z_turn_rst_ps_7_166M_0_arch;

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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:44:17 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_rst_ps_7_166M_0'
1. Summary
----------
SUCCESS in the update of z_turn_rst_ps_7_166M_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 7)) to current project options.

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// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
// IP Revision: 7
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
z_turn_rst_ps_7_166M_0 your_instance_name (
.slowest_sync_clk(slowest_sync_clk), // input wire slowest_sync_clk
.ext_reset_in(ext_reset_in), // input wire ext_reset_in
.aux_reset_in(aux_reset_in), // input wire aux_reset_in
.mb_debug_sys_rst(mb_debug_sys_rst), // input wire mb_debug_sys_rst
.dcm_locked(dcm_locked), // input wire dcm_locked
.mb_reset(mb_reset), // output wire mb_reset
.bus_struct_reset(bus_struct_reset), // output wire [0 : 0] bus_struct_reset
.peripheral_reset(peripheral_reset), // output wire [0 : 0] peripheral_reset
.interconnect_aresetn(interconnect_aresetn), // output wire [0 : 0] interconnect_aresetn
.peripheral_aresetn(peripheral_aresetn) // output wire [0 : 0] peripheral_aresetn
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file z_turn_rst_ps_7_166M_0.v when simulating
// the core, z_turn_rst_ps_7_166M_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>z_turn_rst_ps_7_166M_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">z_turn_rst_ps_7_166M_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">50000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">z_turn_processing_system7_0_0_FCLK_CLK1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../ipshared</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

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# file: z_turn_rst_ps_7_166M_0.xdc
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set_false_path -to [get_pins -hier *cdc_to*/D]

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#--------------------Physical Constraints-----------------

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# (c) Copyright 2012-2015 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 20 -name slowest_sync_clk [get_ports slowest_sync_clk]
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports slowest_sync_clk]

56
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/doc/util_vector_logic_v2_0_changelog.txt Normal file
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2014.4:
* Version 2.0
* Changed the port ordering from (0 to C_SIZE-1) to (C_SIZE-1 downto 0)
* Updated the vhdl library name from util_vector_logic_v1_0 to util_vector_logic_v2_0
2014.1:
* Version 1.0 (Rev. 2)
* Updated the vhdl library name from work to util_vector_logic_v1_0
(c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/sim/z_turn_util_vector_logic_0_0.vhd Normal file
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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY z_turn_util_vector_logic_0_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_util_vector_logic_0_0;
ARCHITECTURE z_turn_util_vector_logic_0_0_arch OF z_turn_util_vector_logic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "not",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
Res => Res
);
END z_turn_util_vector_logic_0_0_arch;

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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY z_turn_util_vector_logic_0_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_util_vector_logic_0_0;
ARCHITECTURE z_turn_util_vector_logic_0_0_arch OF z_turn_util_vector_logic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_util_vector_logic_0_0_arch : ARCHITECTURE IS "z_turn_util_vector_logic_0_0,util_vector_logic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "z_turn_util_vector_logic_0_0,util_vector_logic,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}";
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "not",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
Res => Res
);
END z_turn_util_vector_logic_0_0_arch;

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@ -0,0 +1,16 @@
Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:44:18 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_util_vector_logic_0_0'
1. Summary
----------
SUCCESS in the update of z_turn_util_vector_logic_0_0 (xilinx.com:ip:util_vector_logic:2.0) to current project options.

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// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
// IP Revision: 0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
z_turn_util_vector_logic_0_0 your_instance_name (
.Op1(Op1), // input wire [0 : 0] Op1
.Res(Res) // output wire [0 : 0] Res
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file z_turn_util_vector_logic_0_0.v when simulating
// the core, z_turn_util_vector_logic_0_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

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@ -0,0 +1,47 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>z_turn_util_vector_logic_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="util_vector_logic" spirit:version="2.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OPERATION">not</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">z_turn_util_vector_logic_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPERATION">not</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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2014.4:
* Version 2.0
* Changed the port ordering from (0 to C_SIZE-1) to (C_SIZE-1 downto 0)
* Updated the vhdl library name from util_vector_logic_v1_0 to util_vector_logic_v2_0
2014.1:
* Version 1.0 (Rev. 2)
* Updated the vhdl library name from work to util_vector_logic_v1_0
(c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/sim/z_turn_util_vector_logic_0_1.vhd Normal file
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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY z_turn_util_vector_logic_0_1 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_util_vector_logic_0_1;
ARCHITECTURE z_turn_util_vector_logic_0_1_arch OF z_turn_util_vector_logic_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "not",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
Res => Res
);
END z_turn_util_vector_logic_0_1_arch;

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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY z_turn_util_vector_logic_0_1 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_util_vector_logic_0_1;
ARCHITECTURE z_turn_util_vector_logic_0_1_arch OF z_turn_util_vector_logic_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_util_vector_logic_0_1_arch : ARCHITECTURE IS "z_turn_util_vector_logic_0_1,util_vector_logic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "z_turn_util_vector_logic_0_1,util_vector_logic,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}";
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "not",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
Res => Res
);
END z_turn_util_vector_logic_0_1_arch;

16
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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:44:21 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_util_vector_logic_0_1'
1. Summary
----------
SUCCESS in the update of z_turn_util_vector_logic_0_1 (xilinx.com:ip:util_vector_logic:2.0) to current project options.

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// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
// IP Revision: 0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
z_turn_util_vector_logic_0_1 your_instance_name (
.Op1(Op1), // input wire [0 : 0] Op1
.Res(Res) // output wire [0 : 0] Res
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file z_turn_util_vector_logic_0_1.v when simulating
// the core, z_turn_util_vector_logic_0_1. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

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<spirit:description>Performs bitwise logic operations on two n-bit inputs to produce a single n-bit output </spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_SIZE</spirit:name>
<spirit:displayName>C Size</spirit:displayName>
<spirit:value spirit:format="long"
spirit:resolve="user"
spirit:id="PARAM_VALUE.C_SIZE"
spirit:order="1100">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_OPERATION</spirit:name>
<spirit:displayName>C Operation</spirit:displayName>
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spirit:id="PARAM_VALUE.C_OPERATION"
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sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/doc/util_vector_logic_v2_0_changelog.txt Normal file
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2014.4:
* Version 2.0
* Changed the port ordering from (0 to C_SIZE-1) to (C_SIZE-1 downto 0)
* Updated the vhdl library name from util_vector_logic_v1_0 to util_vector_logic_v2_0
2014.1:
* Version 1.0 (Rev. 2)
* Updated the vhdl library name from work to util_vector_logic_v1_0
(c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

92
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/sim/z_turn_util_vector_logic_1_0.vhd Normal file
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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY z_turn_util_vector_logic_1_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_util_vector_logic_1_0;
ARCHITECTURE z_turn_util_vector_logic_1_0_arch OF z_turn_util_vector_logic_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "not",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
Res => Res
);
END z_turn_util_vector_logic_1_0_arch;

98
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/synth/z_turn_util_vector_logic_1_0.vhd Normal file
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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY z_turn_util_vector_logic_1_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END z_turn_util_vector_logic_1_0;
ARCHITECTURE z_turn_util_vector_logic_1_0_arch OF z_turn_util_vector_logic_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_util_vector_logic_1_0_arch : ARCHITECTURE IS "z_turn_util_vector_logic_1_0,util_vector_logic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "z_turn_util_vector_logic_1_0,util_vector_logic,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}";
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "not",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
Res => Res
);
END z_turn_util_vector_logic_1_0_arch;

16
sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.upgrade_log Normal file
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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015
| Date : Fri Jul 10 13:44:22 2015
| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601)
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'z_turn_util_vector_logic_1_0'
1. Summary
----------
SUCCESS in the update of z_turn_util_vector_logic_1_0 (xilinx.com:ip:util_vector_logic:2.0) to current project options.

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