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harmonize code-style with VILLAScommon/node

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This commit is contained in:
Steffen Vogel 2020-06-11 14:26:38 +02:00
parent c906116d86
commit 6882e9d418
19 changed files with 53 additions and 62 deletions
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4
fpga/gpu/include/villas/gpu.hpp
View file

@ -112,5 +112,5 @@ private:
Logger logger;
};
} // namespace villas
} // namespace gpu
} /* namespace villas */
} /* namespace gpu */

4
fpga/gpu/kernels.hpp
View file

@ -35,5 +35,5 @@ kernel_mailbox(volatile uint32_t *mailbox, volatile uint32_t* counter);
__global__ void
kernel_memcpy(volatile uint8_t* dst, volatile uint8_t* src, size_t length);
} // namespace villas
} // namespace gpu
} /* namespace villas */
} /* namespace gpu */

4
fpga/include/villas/fpga/card.hpp
View file

@ -138,7 +138,7 @@ public:
{ return villas::logging.get("PCIeCardFactory"); }
};
} // namespace fpga
} // namespace villas
} /* namespace fpga */
} /* namespace villas */
/** @} */

11
fpga/include/villas/fpga/ip.hpp
View file

@ -28,8 +28,7 @@
* @{
*/
#ifndef VILLAS_IP_HPP
#define VILLAS_IP_HPP
#pragma once
#include <map>
#include <list>
@ -272,8 +271,6 @@ private:
/** @} */
} // namespace ip
} // namespace fpga
} // namespace villas
#endif // VILLAS_IP_HPP
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */

11
fpga/include/villas/fpga/ip_node.hpp
View file

@ -28,8 +28,7 @@
* @{
*/
#ifndef VILLAS_IP_NODE_HPP
#define VILLAS_IP_NODE_HPP
#pragma once
#include <map>
#include <string>
@ -147,8 +146,6 @@ public:
/** @} */
} // namespace ip
} // namespace fpga
} // namespace villas
#endif // VILLAS_IP_NODE_HPP
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */

6
fpga/include/villas/fpga/ips/aurora.hpp
View file

@ -82,8 +82,8 @@ public:
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

6
fpga/include/villas/fpga/ips/bram.hpp
View file

@ -80,8 +80,8 @@ public:
{ return {"xilinx.com:ip:axi_bram_ctrl:"}; }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

6
fpga/include/villas/fpga/ips/dma.hpp
View file

@ -130,8 +130,8 @@ public:
{ return {"xilinx.com:ip:axi_dma:"}; }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

6
fpga/include/villas/fpga/ips/fifo.hpp
View file

@ -107,8 +107,8 @@ public:
{ return {"xilinx.com:ip:axis_data_fifo:"}; }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

6
fpga/include/villas/fpga/ips/gpu2rtds.hpp
View file

@ -82,6 +82,6 @@ public:
{ return {"acs.eonerc.rwth-aachen.de:hls:gpu2rtds:"}; }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */

6
fpga/include/villas/fpga/ips/hls.hpp
View file

@ -132,6 +132,6 @@ protected:
bool running;
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */

6
fpga/include/villas/fpga/ips/intc.hpp
View file

@ -107,8 +107,8 @@ public:
{ return Vlnv(getCompatibleVlnvString()); }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

6
fpga/include/villas/fpga/ips/pcie.hpp
View file

@ -87,8 +87,8 @@ public:
{ return Vlnv(getCompatibleVlnvString()); }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

6
fpga/include/villas/fpga/ips/rtds.hpp
View file

@ -79,8 +79,8 @@ public:
{ return {"acs.eonerc.rwth-aachen.de:user:rtds_axis:"}; }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

6
fpga/include/villas/fpga/ips/rtds2gpu.hpp
View file

@ -91,6 +91,6 @@ public:
{ return {"acs.eonerc.rwth-aachen.de:hls:rtds2gpu:"}; }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */

5
fpga/include/villas/fpga/ips/rtds2gpu/register_types.hpp
View file

@ -1,5 +1,4 @@
#ifndef REGISTER_TYPES_H
#define REGISTER_TYPES_H
#pragma once
#include <stdint.h>
#include <cstddef>
@ -53,5 +52,3 @@ struct Rtds2GpuMemoryBuffer {
T data[N];
reg_doorbell_t doorbell;
};
#endif // REGISTER_TYPES_H

6
fpga/include/villas/fpga/ips/switch.hpp
View file

@ -94,8 +94,8 @@ public:
{ return Vlnv(getCompatibleVlnvString()); }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

6
fpga/include/villas/fpga/ips/timer.hpp
View file

@ -95,8 +95,8 @@ public:
{ return {"xilinx.com:ip:axi_timer:"}; }
};
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

4
fpga/include/villas/fpga/vlnv.hpp
View file

@ -79,7 +79,7 @@ private:
std::string version;
};
} // namespace fpga
} // namespace villas
} /* namespace fpga */
} /* namespace villas */
/** _FPGA_VLNV_HPP_ @} */