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Add initial Aurora driver
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5 changed files with 76 additions and 10 deletions
3
fpga/.gitignore
vendored
3
fpga/.gitignore
vendored
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@ -4,3 +4,6 @@ build/
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*.o
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*.so
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*.user
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.vscode/
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@ -39,7 +39,6 @@ public:
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static constexpr const char* slavePort = "s_axis";
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void dump();
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double getDt();
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std::list<std::string> getMemoryBlocks() const
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{ return { registerMemory }; }
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@ -34,6 +34,7 @@ set(SOURCES
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ips/dma.cpp
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ips/bram.cpp
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ips/rtds.cpp
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ips/aurora.cpp
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ips/rtds2gpu/rtds2gpu.cpp
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ips/rtds2gpu/xrtds2gpu.c
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64
fpga/lib/ips/aurora.cpp
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64
fpga/lib/ips/aurora.cpp
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/** Driver for wrapper around Aurora (acs.eonerc.rwth-aachen.de:user:aurora)
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*
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* @author Hatim Kanchwala <hatim@hatimak.me>
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* @copyright 2020, Hatim Kanchwala
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <cstdint>
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#include <villas/utils.h>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/ips/aurora.hpp>
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/* Register offsets */
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#define AUR_AXIS_SR_OFFSET 0x00 /**< Status Register (read-only). See AUR_AXIS_SR_* constant. */
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#define AUR_AXIS_CR_OFFSET 0x04 /**< Control Register (read/write) */
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/* Status register bits */
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#define AUR_AXIS_SR_LOOPBACK (1 << 0)/**< ‘1’ when Aurora IP is in loopback mode. */
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/* Control register bits */
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namespace villas {
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namespace fpga {
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namespace ip {
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static AuroraFactory auroraFactoryInstance;
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void Aurora::dump()
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{
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/* Check Aurora AXI4 registers */
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const uint32_t sr = readMemory<uint32_t>(registerMemory, AUR_AXIS_SR_OFFSET);
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logger->info("Aurora-NovaCor AXI-Stream interface details:");
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logger->info("Aurora status: {:#x}", sr);
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logger->info(" Loopback mode: {}", sr & AUR_AXIS_SR_LOOPBACK ? CLR_GRN("yes") : CLR_RED("no"));
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}
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AuroraFactory::AuroraFactory() :
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IpNodeFactory(getName())
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{
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}
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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@ -39,6 +39,7 @@
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#include <villas/fpga/vlnv.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include <villas/fpga/ips/rtds.hpp>
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#include <villas/fpga/ips/aurora.hpp>
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using namespace villas;
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@ -145,17 +146,15 @@ int main(int argc, char* argv[])
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auto card = setupFpgaCard(configFile, fpgaName);
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auto rtds = dynamic_cast<fpga::ip::Rtds*>
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(card->lookupIp(fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")));
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auto aurora = dynamic_cast<fpga::ip::Aurora*>
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(card->lookupIp(fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:aurora:")));
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//auto dma = dynamic_cast<fpga::ip::Dma*>
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// (card->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_dma:")));
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auto dma = dynamic_cast<fpga::ip::Dma*>
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(card->lookupIp("hier_0_axi_dma_axi_dma_1"));
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if(rtds == nullptr) {
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logger->error("No RTDS interface found on FPGA");
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if(aurora == nullptr) {
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logger->error("No Aurora interface found on FPGA");
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return 1;
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}
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@ -164,13 +163,13 @@ int main(int argc, char* argv[])
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return 1;
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}
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rtds->dump();
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aurora->dump();
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rtds->connect(rtds->getMasterPort(rtds->masterPort),
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aurora->connect(aurora->getMasterPort(aurora->masterPort),
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dma->getSlavePort(dma->s2mmPort));
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dma->connect(dma->getMasterPort(dma->mm2sPort),
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rtds->getSlavePort(rtds->slavePort));
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aurora->getSlavePort(aurora->slavePort));
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auto &alloc = villas::HostRam::getAllocator();
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auto mem = alloc.allocate<int32_t>(0x100 / sizeof(int32_t));
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