66f44c8ba4
fix: Formatting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-11-03 10:52:12 +01:00
Niklas Eiling
a96ba9b9d8
fix comments in memory, ethercat and rtp
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-10-31 12:45:09 +01:00
3e483de030
more checks against errors
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
Co-authored-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-10-31 12:45:09 +01:00
11069e782b
use CLOCK_MONOTONIC
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
Co-authored-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-10-31 12:45:09 +01:00
60b397dc29
Remove broken opal node-type
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-10-31 11:07:52 +01:00
Steffen Vogel
28d354cb84
Fix formatting with clang-format
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-10-15 19:31:49 +02:00
Philipp Jungkamp
40440f2466
ethercat: Shuffle includes to fix failing Nix builds
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Signed-off-by: Philipp Jungkamp <p.jungkamp@gmx.net>
2024-08-28 23:20:52 +02:00
Niklas Eiling
7e1bad3590
fpga: Use float accessor for reading and writing floats
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This fixes breaking strict aliasing rules.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
36687d6af4
fpga: fix debug output
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
b52f445a52
fpga: handle receving more data than size of configured signals
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
9b79c16fb3
fpga: make FPGA support sending and receiving integers
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
0582a27ee0
fix: Remove dead code from iec61850 SV node-type
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-08-21 12:41:07 +02:00
90ce4a0fe7
fix(iec61850-9-2): Fix Sampled Values node-type for NEIS paper
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-08-13 13:26:08 +02:00
Niklas Eiling
f25e1dd689
log: fix undefined intitialization order of static objects. fixes #799 .
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-05 14:57:13 +02:00
Niklas Eiling
7128da24c3
fpga: make dma able to handle sequence numbers generated in the FPGA
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Niklas Eiling
d2c1f55f21
fpga: fix timestep being hardcoded
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Niklas Eiling
675c489126
fpga: switch to float accessor for writes
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Niklas Eiling
f84e0691f1
fpga: fix redundant return in getPollFD
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-06 09:29:29 +02:00
Niklas Eiling
7ef44a4911
fpga: do not return poll FDs if we are not using FDs
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-06 09:29:29 +02:00
Niklas Eiling
584712300d
fpga: fix wrong unpack string for config parsing
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-06 09:29:29 +02:00
Niklas Eiling
50bc9d9510
fpga: use snake case for low_latency_mode
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
296b7d873a
fpga: improve comments and removed dead code
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
b74ebd391f
fpga: remove output from performance critical code
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
0c3a9f4729
fpga: convert SignalType to string before printing
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
34bca6826b
fpga: make dino sampling rate configurable at top level and via json
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
cc44595f98
test_rtt: Fix possible use of uninitialized variable
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
63337efdd7
test_rtt: Add missing cooldown phase in runtime estimation
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
c10fcc5bd4
test_rtt: Fix logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
aee96e846f
webrtc: Improve logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
b0680bb5cf
test_rtt: Fix compiler errors
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
54d7cf0620
webrtc: Show connection details
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
2e00453f7b
test_rtt: Improve handling of defaults
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
c4afbf5453
test_rtt: Print estimated test durations
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
f6c7434a61
test_rtt: Rework calculation of test duration
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
64749223e8
test_rtt: Improve statistics
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
139101c447
webrtc: Enable ICE TCP
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
047fca5561
test_rtt: Another round of new features
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
bc14304f5e
test_rtt: Fix wrong option identifier
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
a366b80109
Fix formatting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
cad2da3a59
iec61850_sv: Fix IEC 61850-9-2 Sampled Values node and unit test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
84f0ea9cb5
test_rtt: Fix test case numbering
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
bc95217766
test_rtt: Stop test cases properly in order to close file handles
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
1748f433fe
webrtc: Fix libdatachannel version detection
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
Niklas Eiling
f1776f8be4
fpga: improve comments for fastRead and fastWrite
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
a2ff0aca43
fix formatting in fpga
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
9cf926d84e
fpga: add lowLatencyMode setting
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This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d
fpga: improve dma latency
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
2529c7b2d7
Remove superfluous includes
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 18:56:28 +02:00
718f6ca7eb
test_rtt: Fix cppcheck warnings
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
7f8f7023b4
test_rtt: Port to C++
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
