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82 commits

Author SHA1 Message Date
Niklas Eiling
cb085dbe23 log: fix undefined intitialization order of static objects. fixes #799. 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-08-05 12:33:26 +02:00
Niklas Eiling
34bca6826b fpga: make dino sampling rate configurable at top level and via json 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Steffen Vogel
936830d484 Remove unused includes and variables 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-03-27 17:22:07 +01:00
Steffen Vogel
535d64a644 Replace last tab indentation with spaces 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-02-29 23:18:47 +01:00
Steffen Vogel
4b36073711 Use spaces for indention of CMake files 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-02-29 23:18:47 +01:00
Steffen Vogel
3d73c759ea Reformat all code with clang-format 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-02-29 19:34:27 +01:00
Niklas Eiling
a0fc73f2ee villas-fpga-ctrl: return to old loggers 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
7c6d350eb0 format and increase robustness of interuppt handling 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
b2fcfeaa67 move more of the switch configuration boilerplate into ConnectString 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-12 11:46:59 +01:00
Niklas Eiling
ca6c70e09b ConnectString: Make channel data type more generic 
we can not only connect Aurora channels to the switch so use Node
instead as the data type

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-12 11:46:59 +01:00
Niklas Eiling
1c2d8e440b update and reformat villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
7ce1ee5a6c make villas-fpga-ctrl accept multiple connect strings 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Steffen Vogel
157d5b21d7 Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82) 
This edits the headers in every file so the copyright notice mentions RWTH Aachen University. We also update some copyright years and fix various comments so the header is the same across all of VILLASframework.

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

---------

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-09-08 11:35:18 +02:00
Niklas Eiling
a5991bc794 deactivate stric-aliasing for cast 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-07-25 18:26:19 +02:00
Niklas Eiling
b05910f24e add C bindings for external use of VILLASfpga 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 17:12:47 +01:00
Niklas Eiling
7847658548 fix output formatting not being able to print numbers larger than 9 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 15:35:38 +01:00
Niklas Eiling
e6f34f83f4 make villas-fpga-pipe use separat memory segments for reading and writing 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 12:10:37 +01:00
Niklas Eiling
4ef114fad4 remove unnecessary characters in villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 10:23:13 +01:00
Niklas Eiling
6b58624e57 fix villas-fpga-pipe 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-15 16:11:44 +01:00
Niklas Eiling
87968ab73e enable reading from stdin to DMA in villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
1e3294d14c start readFromDmaToStdOut in separate thread 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
e6f035cd31 add basic thread-safety to ips/dma 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
590cef10d0 add check for missed interrupts when handling reads 
introduce new struct Completion that is returned by Dma::readCompletion
and Dma::writeCompletion

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
ab39f57405 add more configuration options to villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
ce1e8e28ce move formatting of printing to stdout to separate class and make in configurable 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
498af9fd1c ips/dma: make read correctly wait on interrupts 
Modify villas-fpga-ctrl to fit the new behavior of Dma.
Makes reading from DMA work even when we are too slow and
only receive partial batches of BDs.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
14f924b6c5 rework MemoryBlock use to make use of shared_ptr so the lifetime of the objects is properly tracked 
this fixes that the wrong order of allocating and PciCard destruction
causes an undefined state.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:09:09 +01:00
Niklas Eiling
40d0452b0a move connectString parsing into separate class 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:02:32 +01:00
Niklas Eiling
b66733640a format and comment fixes 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:02:32 +01:00
Steffen Vogel
ea5ab4ed5d fix broken CMakeLists 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:21:05 +01:00
Steffen Vogel
94cf3583d8 fix naming of fpgaHelper file 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 08:11:35 +01:00
Steffen Vogel
9b27c31b9c fixup copyright texts 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:32:48 +01:00
Steffen Vogel
f776cba693 relicense project to Apache 2.0 
The project is now also REUSE compliant: https://reuse.software/
Previous copyright holders have provided their
acknowledgement to transition to the new license in the
following GitHub PR: https://github.com/VILLASframework/fpga/pull/66

Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:20:15 +01:00
Niklas Eiling
4785146a4c fix villas-fpga-cat and villas-fpga-xbar-select scripts to use villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-05 12:30:36 +01:00
Niklas Eiling
a818bc0b64 combine functionalities of binaries into a single one 
combine what was previously achieved by the separate binaries
villas-fpga-xbar-select and villas-fpga-cat into a single new
binary villas-fpga-ctl. Here we can select crossbar connections
via command line parameters. To avoid regression there are shell
scripts providing the old functionalities directly.

Currently the villas-fpga-pipe functionality is not supported,
because we still need to implement stdin input and routing that
to the fpga.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-04 17:16:35 +01:00
Pascal Bauer
56dcf9fac6 add comment to suppress casting warning 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2022-12-19 15:47:36 +01:00
Pascal Bauer
1c85a4330f cast voidpointer to uint for arithmetik 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2022-12-19 15:47:36 +01:00
Pascal Bauer
6a8acc467b changed casting from intmax to uintmax 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2022-12-19 15:47:35 +01:00
Steffen Vogel
92ab5d078f remove aliases for smart pointers and lists 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2022-12-07 19:04:47 +01:00
Niklas Eiling
404bc9c8be fix throwing an error in villas-fpga-cat leading to abort, because of wrong deconstructor order 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2022-12-03 15:16:24 +01:00
Niklas Eiling
f26656a90d bump common subrepo, use debug logging in villas-fpga-cat 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2022-12-02 13:52:32 +01:00
Niklas Eiling
0d0aae090d add villas-fpga-xbar-select; improve DMA parameters in ips/dma 2022-11-29 14:51:54 +01:00
Niklas Eiling
6a900ba5e4 fix villas-fpga-cat interpreting floats wrong 2022-11-29 14:51:54 +01:00
Niklas Eiling
f105b08144 clean up and comment ips/dma.cpp 2022-11-29 14:51:53 +01:00
Niklas Eiling
34c8458500 villas-fpga-cat: fix double value being constructed wrong 2022-11-29 14:51:53 +01:00
Niklas Eiling
fb48e36a0b add villas-fpga-cat app that outputs a stream of data 2022-11-29 14:51:53 +01:00
Niklas Eiling
e029963839 move helper functions from villas-fpga-pipe into separate file 2022-11-29 14:51:53 +01:00
Steffen Vogel
3f8a38adce dma: first successful test with scatter gather 
(Aurora IPs still broken?)
 2022-10-28 11:32:01 -04:00
Steffen Vogel
dbf25a6d8e adapt villas-fpga-pipe to new DMA code 2022-10-28 08:19:00 -04:00
Steffen Vogel
0e0197a3be fix coding style 2022-10-28 08:03:57 -04:00