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6286 commits 171 branches 31 tags 76 MiB
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644 commits

Author SHA1 Message Date
Niklas Eiling
7847658548 fix output formatting not being able to print numbers larger than 9 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 15:35:38 +01:00
Niklas Eiling
e6f34f83f4 make villas-fpga-pipe use separat memory segments for reading and writing 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 12:10:37 +01:00
Niklas Eiling
4ef114fad4 remove unnecessary characters in villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 10:23:13 +01:00
Niklas Eiling
6b58624e57 fix villas-fpga-pipe 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-15 16:11:44 +01:00
Niklas Eiling
cbad1ca9d1 ConnectString: also allow pipe as a connection target 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-15 16:11:44 +01:00
Pascal Henry Bauer
3db2005bbf removed duplicated declarations 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-02-10 13:34:20 +01:00
Pascal Henry Bauer
26e2251afe reorder of members and added virtual 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-02-10 13:34:20 +01:00
Pascal Henry Bauer
85b2e8b030 removed duplicate implementation 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-02-10 13:34:20 +01:00
Niklas Eiling
c80e5c083d remove map and umapmemoryblock from PcieCard 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:26:11 +01:00
Niklas Eiling
10ecf6c9a6 fix memoryBlocksMapped being defined in both Card and PcieCard 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:18:42 +01:00
Niklas Eiling
87968ab73e enable reading from stdin to DMA in villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
1e3294d14c start readFromDmaToStdOut in separate thread 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
62cab0c4dc clean up README.md 
add project description and related projects (MIOB and DINO)

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
e6f035cd31 add basic thread-safety to ips/dma 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
590cef10d0 add check for missed interrupts when handling reads 
introduce new struct Completion that is returned by Dma::readCompletion
and Dma::writeCompletion

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
ab39f57405 add more configuration options to villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
8ff0370d36 fix license of utils.hpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
ce1e8e28ce move formatting of printing to stdout to separate class and make in configurable 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
498af9fd1c ips/dma: make read correctly wait on interrupts 
Modify villas-fpga-ctrl to fit the new behavior of Dma.
Makes reading from DMA work even when we are too slow and
only receive partial batches of BDs.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
5ab6007909 small code review 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:10 +01:00
Niklas Eiling
14f924b6c5 rework MemoryBlock use to make use of shared_ptr so the lifetime of the objects is properly tracked 
this fixes that the wrong order of allocating and PciCard destruction
causes an undefined state.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:09:09 +01:00
Niklas Eiling
40d0452b0a move connectString parsing into separate class 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:02:32 +01:00
Niklas Eiling
b66733640a format and comment fixes 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:02:32 +01:00
Niklas Eiling
418a8dc7a9 fix segfault in card because vfioContainer was shadowed in PcieCard 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:02:13 +01:00
Pascal Henry Bauer
f81a1ddc6d moved destructor to base class 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-27 16:57:31 +01:00
Pascal Henry Bauer
2a9db48888 fixed wrong name in comment 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-27 15:53:05 +01:00
Pascal Henry Bauer
7f2ed2180d fixed formatting 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-27 14:04:22 +01:00
Pascal Henry Bauer
6de526c894 fixed formatting 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-27 13:59:45 +01:00
Pascal Henry Bauer
3587ccc0fa change pciecard name to pcie_card 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
9be5c3c274 removed duplicate inherited members 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
6b87c9bc30 refactor to use pcie card (Legacy) 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
e8b593cf1f added card definitions 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
0dd52db44d add card header declarations 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
22244fed04 add include guard 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
dfb4d30b3f added namespace 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
7534086e08 change core to use base class card over pcieclass 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
ae944b6ce3 added copyright information 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
a10e568777 added pcieclass to buildsystem 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
d2d7f9430d moved pciecard to own file 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
e254e7cfe6 move card class to own file 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 17:08:19 +01:00
Steffen Vogel
62af43f25e update libxil submodule 
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-01-11 09:40:23 +01:00
Steffen Vogel
8741f39029 fix cppcheck error 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:35:44 +01:00
Steffen Vogel
ea5ab4ed5d fix broken CMakeLists 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:21:05 +01:00
Steffen Vogel
94cf3583d8 fix naming of fpgaHelper file 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 08:11:35 +01:00
Steffen Vogel
8376508b6e fix copyright notices in license files 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 08:10:12 +01:00
Steffen Vogel
63f3463b54 fix attribution to Daniel 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 08:08:40 +01:00
Steffen Vogel
1c6779287b remove old Doxygen comments 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:33:54 +01:00
Steffen Vogel
9b27c31b9c fixup copyright texts 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:32:48 +01:00
Steffen Vogel
8a71542d4f run reuse linter in CI 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:24:05 +01:00
Steffen Vogel
f776cba693 relicense project to Apache 2.0 
The project is now also REUSE compliant: https://reuse.software/
Previous copyright holders have provided their
acknowledgement to transition to the new license in the
following GitHub PR: https://github.com/VILLASframework/fpga/pull/66

Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:20:15 +01:00