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10 commits

Author SHA1 Message Date
Pascal Bauer
e6524f944f ignore type errors
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-07-29 16:14:26 +02:00
Pascal Bauer
81cb364d1f add module "dinoif_fast_nologic"
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-07-29 16:14:26 +02:00
Niklas Eiling
ca03e1d406 fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
1560f67656 Reformat Python code with black
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
a2abaa3cda Merge project files, scripts and CMake files of VILLASfpga
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 19:33:23 +01:00
3397bca19b remove some obsolete scripts 2018-04-05 10:22:46 +02:00
e0959b562f hwdef-parse: parse baseaddr and size of BRAM instances in the design 2017-11-21 18:42:27 +01:00
5ba80c171d hwdef-parse: remove debug output 2017-11-21 18:42:01 +01:00
502e1f797a hwdef-parse: fix errors found by parsing more complex villas hwdef 2017-11-21 18:41:42 +01:00
857c5c2056 added hwdef-parse.py 2017-11-21 18:04:45 +01:00