Niklas Eiling
48b0e85565
fpga: fix redundant return in getPollFD
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
b5cd0e530c
fpga: do not return poll FDs if we are not using FDs
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
b4ef71aa74
fpga: fix wrong unpack string for config parsing
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
6180e1019d
fpga: use snake case for low_latency_mode
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
8320e4f7c3
fpga: improve comments and removed dead code
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
c4d2468268
fpga: remove output from performance critical code
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
851f66050c
fpga: convert SignalType to string before printing
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
1e0bfa9b73
fpga: make dino sampling rate configurable at top level and via json
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
4be302b480
test_rtt: Fix possible use of uninitialized variable
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
937242ca84
test_rtt: Add missing cooldown phase in runtime estimation
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0765e456fa
test_rtt: Fix logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
6c6d37d00d
webrtc: Improve logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
7848dd7019
test_rtt: Fix compiler errors
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
6114f6dcc2
webrtc: Show connection details
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
69b00f8915
test_rtt: Improve handling of defaults
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
b4b86aa220
test_rtt: Print estimated test durations
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0601ede07b
test_rtt: Rework calculation of test duration
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
19982bf49b
test_rtt: Improve statistics
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
f75bf8536c
webrtc: Enable ICE TCP
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
6efaa9e55b
test_rtt: Another round of new features
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
f695225a3a
test_rtt: Fix wrong option identifier
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
7f857f392c
Fix formatting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
ffe804e177
iec61850_sv: Fix IEC 61850-9-2 Sampled Values node and unit test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0ae86790b6
test_rtt: Fix test case numbering
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
d0b9bd5935
test_rtt: Stop test cases properly in order to close file handles
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
59a76927fd
webrtc: Fix libdatachannel version detection
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
0ae08e8434
fpga: improve comments for fastRead and fastWrite
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
98c1f36a02
fix formatting in fpga
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
87a1628c4a
fpga: add lowLatencyMode setting
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This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
f67ca37b0c
fpga: improve dma latency
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
a7d24f756f
Remove superfluous includes
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
a5487f4210
test_rtt: Fix cppcheck warnings
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
55238f58b9
test_rtt: Port to C++
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
5ffc0f92f0
test_rtt: Show test process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
d4bc2409c3
Fix some typos and harmonize log output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
3326499e19
Harmonize descriptions of plugins
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
6c5e29de68
webrtc: Fix several TODOs and other smaller tweaks
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
714db711db
Remove unused includes and variables
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
ef27de2d6f
rtp: Fix headers
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
1e6c714560
compat: Update reliability PAI for libdatachannel >= 0.20
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
43a9ab532a
rtp: Upgrade libre dependency to v3.6.0
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
d9b3bdb0de
fpga: DMA: poll BD instead of hardware register
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polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
cc5cd1cbed
fpga: do not create the vfio container twice
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Steffen Vogel
250d016a98
mqtt: Do not attempt validating topics if they are not set
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-06-18 12:39:42 +02:00
dc436073a2
Use spaces for indention of C++ comments
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
4b36073711
Use spaces for indention of CMake files
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
bc670254e2
file: Make directories listable when created
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 22:34:35 +01:00
9247846805
exec: Pass name of node and config path via environment variable to sub-process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-27 19:19:27 +01:00
Niklas Eiling
49523a5076
fpga: remove std::filesystem and properly retrieve searchPath from
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configPath
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
ea0bfcf7f4
fpga: clean up debug outputs
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
