Niklas Eiling
7e1bad3590
fpga: Use float accessor for reading and writing floats
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This fixes breaking strict aliasing rules.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
9b79c16fb3
fpga: make FPGA support sending and receiving integers
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
296b7d873a
fpga: improve comments and removed dead code
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
34bca6826b
fpga: make dino sampling rate configurable at top level and via json
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
c151be5cca
fpga: fix includes and various comments
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
9cf926d84e
fpga: add lowLatencyMode setting
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This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d
fpga: improve dma latency
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
18aa0c8862
rework fpga node type
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The various changes in fpga require a rewrite of the fpga node type.
To allow relative paths for the fpga config file, Config and SuperNode
had to be modified so they store the path of the main config file.
The syntax of the fpga node type configuration has changed - the example
config in etc has been modified accordingly.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Steffen Vogel
02a2aa4f94
Apply clang-format changes
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-08 11:37:42 +02:00
68654f95f2
Add periods after file headers and fix email addresses
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-09-07 11:16:04 +02:00
Steffen Vogel
0735eb0f89
Make project REUSE compliant
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And various other cleanups and harmonizations
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-07 11:16:04 +02:00
Steffen Vogel
78727be952
Use C++ style comments
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-07 11:16:04 +02:00
Niklas Eiling
554515fe30
fix fpga node type to work with current fpga master
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2023-07-25 18:16:51 +02:00
Philipp Jungkamp
f73efabd18
Adapt fpga node to changed uuid passing
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-06-30 11:30:05 +02:00
Steffen Vogel
7749a3a922
No not pass super-node UUID to Node::parse() any longer
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 10:51:01 +02:00
Steffen Vogel
d57a5d3306
Refactor parameter name for parse() from cfg to json
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 10:48:43 +02:00
3b5f686262
code-style fixes
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:10:02 +01:00
ae17d58cc4
fpga: remove unused code
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:10:02 +01:00
1c7d57d5f5
fpga: do not reset VFIO container by hand
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We can rely on the Dtor of the global shared_ptr to destruct the container
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:10:02 +01:00
39825a8034
fpga: fix factory
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:10:02 +01:00
9a4f8a0b19
fpga: first compiling version
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:09:35 +01:00
de9bda4d74
fpga: fix syntax errors
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:09:35 +01:00
7eec1bb753
update Steffens mail address
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-16 23:44:07 +01:00
b94746effb
relicense VILLASnode to Apache 2.0
2022-07-04 18:23:57 +02:00
11a25f6fb7
update mail address
2022-03-15 09:29:20 -04:00
17ac92aa21
update copyright year
2022-03-15 09:28:57 -04:00
784e970bfe
port large parts of VILLASnode to C++ and fix tests alongside
2022-01-11 09:19:53 -05:00
00a9e92b0a
remove old plugin code
2021-06-21 16:11:42 -04:00
731909c3a8
ported io/format code to C++
2021-06-17 08:26:46 -04:00
4f370ee1b2
drop legacy logger
2021-03-17 14:58:45 +00:00
3c13f67930
refactor: struct node -> struct vnode
2020-09-10 17:40:36 +02:00
a5bc8eb90f
fpga: first compiling code of fpga support
2020-07-01 17:07:16 +02:00
