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315 commits

Author SHA1 Message Date
Niklas Eiling
e93b8e998d fix IPs without stream port causing an error and fix formatting in 
node.cpp

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
bd1f32da7b fix fomatting in core.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
7e07da6e60 add i2c ip draft 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
d61337023e add draft for i2c drvier implementation 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:17:26 +01:00
Niklas Eiling
2967fb8ac9 fix fpga.cpp unit test failing due to changed DeviceList interface 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Niklas Eiling
654ee84e9e make FPGA device interface agnostic 
remove explicit mentioning of PCIe in the use of Device as a preparation
for integrating platform devices. auto formatted some files.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Philipp Jungkamp
e2c2ec2c8b Fix fmt 10.0.0 related formatting errors. 
Signed-off-by: Philipp Jungkamp <p.jungkamp@gmx.net>
 2023-09-26 17:00:31 +02:00
Steffen Vogel
157d5b21d7 Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82) 
This edits the headers in every file so the copyright notice mentions RWTH Aachen University. We also update some copyright years and fix various comments so the header is the same across all of VILLASframework.

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

---------

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-09-08 11:35:18 +02:00
Niklas Eiling
d9993409e0 fix possible NULL dereferencing in villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 14:56:54 +01:00
Niklas Eiling
9d4cd5384d clean up debuggin output and fix scanf usage in villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:52:36 +01:00
Niklas Eiling
d273162f71 fix PCIeCardFactory looking for IP config file at the wrong location 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:29:32 +01:00
Niklas Eiling
d9e60e22b1 make it possible to specify a search path in PcieCard::make so we can use relative paths in config files 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:15:25 +01:00
Niklas Eiling
c05ae4d282 add C bindings for DMA interactions and add a test/example 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 10:47:45 +01:00
Niklas Eiling
b05910f24e add C bindings for external use of VILLASfpga 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 17:12:47 +01:00
Niklas Eiling
7847658548 fix output formatting not being able to print numbers larger than 9 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 15:35:38 +01:00
Niklas Eiling
6b58624e57 fix villas-fpga-pipe 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-15 16:11:44 +01:00
Niklas Eiling
cbad1ca9d1 ConnectString: also allow pipe as a connection target 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-15 16:11:44 +01:00
Pascal Henry Bauer
85b2e8b030 removed duplicate implementation 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-02-10 13:34:20 +01:00
Niklas Eiling
c80e5c083d remove map and umapmemoryblock from PcieCard 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:26:11 +01:00
Niklas Eiling
e6f035cd31 add basic thread-safety to ips/dma 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
590cef10d0 add check for missed interrupts when handling reads 
introduce new struct Completion that is returned by Dma::readCompletion
and Dma::writeCompletion

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
ab39f57405 add more configuration options to villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
498af9fd1c ips/dma: make read correctly wait on interrupts 
Modify villas-fpga-ctrl to fit the new behavior of Dma.
Makes reading from DMA work even when we are too slow and
only receive partial batches of BDs.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
5ab6007909 small code review 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:10 +01:00
Niklas Eiling
14f924b6c5 rework MemoryBlock use to make use of shared_ptr so the lifetime of the objects is properly tracked 
this fixes that the wrong order of allocating and PciCard destruction
causes an undefined state.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:09:09 +01:00
Niklas Eiling
40d0452b0a move connectString parsing into separate class 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:02:32 +01:00
Niklas Eiling
b66733640a format and comment fixes 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:02:32 +01:00
Pascal Henry Bauer
f81a1ddc6d moved destructor to base class 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-27 16:57:31 +01:00
Pascal Henry Bauer
7f2ed2180d fixed formatting 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-27 14:04:22 +01:00
Pascal Henry Bauer
3587ccc0fa change pciecard name to pcie_card 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
6b87c9bc30 refactor to use pcie card (Legacy) 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
e8b593cf1f added card definitions 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
7534086e08 change core to use base class card over pcieclass 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
ae944b6ce3 added copyright information 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
a10e568777 added pcieclass to buildsystem 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
d2d7f9430d moved pciecard to own file 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
e254e7cfe6 move card class to own file 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-01-26 17:08:19 +01:00
Steffen Vogel
94cf3583d8 fix naming of fpgaHelper file 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 08:11:35 +01:00
Steffen Vogel
9b27c31b9c fixup copyright texts 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:32:48 +01:00
Steffen Vogel
f776cba693 relicense project to Apache 2.0 
The project is now also REUSE compliant: https://reuse.software/
Previous copyright holders have provided their
acknowledgement to transition to the new license in the
following GitHub PR: https://github.com/VILLASframework/fpga/pull/66

Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:20:15 +01:00
Steffen Vogel
53ddbe4e10 refactor registration of IP core drivers to be aligned with registration of VILLASnode formats and node-types 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-05 14:21:20 +01:00
Niklas Eiling
c6a2629dff remove redundant and wrong comment 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-05 14:03:36 +01:00
Niklas Eiling
80af655ac5 make DMA ip unmap memory owned by itself 
unmapping of the scatter gather attribute memory was done
after the DMA destructor was called, leading to Card trying to
unmap memory that was already freed.
This lead to crashing during cleaning up.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-04 17:17:21 +01:00
Niklas Eiling
a818bc0b64 combine functionalities of binaries into a single one 
combine what was previously achieved by the separate binaries
villas-fpga-xbar-select and villas-fpga-cat into a single new
binary villas-fpga-ctl. Here we can select crossbar connections
via command line parameters. To avoid regression there are shell
scripts providing the old functionalities directly.

Currently the villas-fpga-pipe functionality is not supported,
because we still need to implement stdin input and routing that
to the fpga.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-04 17:16:35 +01:00
Niklas Eiling
f5b0762b1a make memory manager destroy IP objects and improve DMA logging 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-04 11:04:48 +01:00
Pascal Bauer
082dd40edb added class name before virtual method 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2022-12-19 15:47:36 +01:00
Pascal Bauer
c77d124682 fixed allocation order 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2022-12-19 15:47:36 +01:00
Pascal Bauer
a2b8b2942e fixed memory leak (missing deletes before return) 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2022-12-19 15:47:35 +01:00
Steffen Vogel
dee5b2d81f update Steffens mail address 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2022-12-14 17:44:17 +01:00
Steffen Vogel
92ab5d078f remove aliases for smart pointers and lists 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2022-12-07 19:04:47 +01:00