2529c7b2d7
Remove superfluous includes
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 18:56:28 +02:00
Niklas Eiling
c644c8f630
fpga: DMA: poll BD instead of hardware register
...
polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Niklas Eiling
322cdf9639
fpga: do not create the vfio container twice
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Niklas Eiling
49523a5076
fpga: remove std::filesystem and properly retrieve searchPath from
...
configPath
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
ea0bfcf7f4
fpga: clean up debug outputs
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
26e22ca6f4
fpga: make implementation compatible with new createCard interface
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
47362ccede
fpga: enable inline config of card
...
additionally to configuring the card in a separate block, we need to be
able to configure the card from the node config to enable libvillas
users to use the fpga node-type.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Steffen Vogel
226ccecd19
Remove usage of std::filesystem
...
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-26 17:10:57 +01:00
Niklas Eiling
4ca9c88bd0
fpga: add note about wrong cast
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
97a391c271
update fpga submodule
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
18aa0c8862
rework fpga node type
...
The various changes in fpga require a rewrite of the fpga node type.
To allow relative paths for the fpga config file, Config and SuperNode
had to be modified so they store the path of the main config file.
The syntax of the fpga node type configuration has changed - the example
config in etc has been modified accordingly.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Steffen Vogel
02a2aa4f94
Apply clang-format changes
...
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-08 11:37:42 +02:00
68654f95f2
Add periods after file headers and fix email addresses
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-09-07 11:16:04 +02:00
Steffen Vogel
0735eb0f89
Make project REUSE compliant
...
And various other cleanups and harmonizations
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-07 11:16:04 +02:00
Niklas Eiling
554515fe30
fix fpga node type to work with current fpga master
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2023-07-25 18:16:51 +02:00
Philipp Jungkamp
f73efabd18
Adapt fpga node to changed uuid passing
...
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-06-30 11:30:05 +02:00
Steffen Vogel
7749a3a922
No not pass super-node UUID to Node::parse() any longer
...
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 10:51:01 +02:00
Steffen Vogel
d57a5d3306
Refactor parameter name for parse() from cfg to json
...
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 10:48:43 +02:00
Steffen Vogel
a37b64111f
fpga: call base-class function for NodeFactory::start()
...
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-21 11:48:04 +02:00
Steffen Vogel
f6789e4739
fix broken VILLASfpga node-type
...
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-01-13 11:28:53 +01:00
Manuel Pitz
c4bce72c04
make compatible to fmt version 9.0.3
...
Signed-off-by: Manuel Pitz <manuel.pitz@eonerc.rwth-aachen.de>
2023-01-11 12:11:57 +01:00
Steffen Vogel
7d982e12b3
fpga: fix cppcheck warnings
...
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-01-10 16:31:01 +00:00
5398006734
fpga: fix creation of VFIO container
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:10:02 +01:00
3b5f686262
code-style fixes
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:10:02 +01:00
ae17d58cc4
fpga: remove unused code
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:10:02 +01:00
1c7d57d5f5
fpga: do not reset VFIO container by hand
...
We can rely on the Dtor of the global shared_ptr to destruct the container
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:10:02 +01:00
20ffee08e4
fpga: improve code style
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:10:02 +01:00
9a4f8a0b19
fpga: first compiling version
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:09:35 +01:00
de9bda4d74
fpga: fix syntax errors
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-09 11:09:35 +01:00
7eec1bb753
update Steffens mail address
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-16 23:44:07 +01:00
b94746effb
relicense VILLASnode to Apache 2.0
2022-07-04 18:23:57 +02:00
11a25f6fb7
update mail address
2022-03-15 09:29:20 -04:00
17ac92aa21
update copyright year
2022-03-15 09:28:57 -04:00
b402048082
add support for plugin sub-registries
2022-03-04 03:47:46 -05:00
784e970bfe
port large parts of VILLASnode to C++ and fix tests alongside
2022-01-11 09:19:53 -05:00
f5d41edfe3
fpga: fix compilation errors
2021-09-13 15:08:19 +02:00
00a9e92b0a
remove old plugin code
2021-06-21 16:11:42 -04:00
731909c3a8
ported io/format code to C++
2021-06-17 08:26:46 -04:00
4f370ee1b2
drop legacy logger
2021-03-17 14:58:45 +00:00
baddec2228
fix a lot of small bugs
2020-09-10 17:41:30 +02:00
6411fc5ca7
warn about unused return values for *_{init,destroy}() functions
2020-09-10 17:41:29 +02:00
3c13f67930
refactor: struct node -> struct vnode
2020-09-10 17:40:36 +02:00
0e0250dcba
check if struct sample::signals is set everywhere properly
2020-07-06 15:07:05 +02:00
8de965d93d
ci: fix compiler error
2020-07-06 14:03:45 +02:00
547ff5e199
fpga: fix comparison of signed/unsigned ints
2020-07-03 10:04:51 +02:00
a5bc8eb90f
fpga: first compiling code of fpga support
2020-07-01 17:07:16 +02:00
