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1155 commits

Author SHA1 Message Date
718f6ca7eb test_rtt: Fix cppcheck warnings
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
7f8f7023b4 test_rtt: Port to C++
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
0b04f4fd39 test_rtt: Show test process
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
3023ddaa3a Fix some typos and harmonize log output
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
a2d55a9b6e Harmonize descriptions of plugins
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:06:15 +02:00
93cbc5d518 webrtc: Fix several TODOs and other smaller tweaks
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:02:55 +02:00
936830d484 Remove unused includes and variables
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
8db66e25c1 rtp: Fix headers
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
553f01d131 compat: Update reliability PAI for libdatachannel >= 0.20
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
5e70fc38fd rtp: Upgrade libre dependency to v3.6.0
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-26 13:01:15 +01:00
Niklas Eiling
c644c8f630 fpga: DMA: poll BD instead of hardware register
polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Niklas Eiling
322cdf9639 fpga: do not create the vfio container twice
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Steffen Vogel
576df42e42 mqtt: Do not attempt validating topics if they are not set
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-03-12 13:20:32 +01:00
dc436073a2 Use spaces for indention of C++ comments
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
4b36073711 Use spaces for indention of CMake files
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
bc670254e2 file: Make directories listable when created
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 22:34:35 +01:00
9247846805 exec: Pass name of node and config path via environment variable to sub-process
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-27 19:19:27 +01:00
Niklas Eiling
49523a5076 fpga: remove std::filesystem and properly retrieve searchPath from
configPath

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
ea0bfcf7f4 fpga: clean up debug outputs
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
26e22ca6f4 fpga: make implementation compatible with new createCard interface
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
47362ccede fpga: enable inline config of card
additionally to configuring the card in a separate block, we need to be
able to configure the card from the node config to enable libvillas
users to use the fpga node-type.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Steffen Vogel
226ccecd19 Remove usage of std::filesystem
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-26 17:10:57 +01:00
Steffen Vogel
272a3fac36 Fix include order
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
Steffen Vogel
c1410ef8a8 Fix formatting using clang-format
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
Niklas Eiling
4ca9c88bd0 fpga: add note about wrong cast
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
97a391c271 update fpga submodule
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
18aa0c8862 rework fpga node type
The various changes in fpga require a rewrite of the fpga node type.
To allow relative paths for the fpga config file, Config and SuperNode
had to be modified so they store the path of the main config file.
The syntax of the fpga node type configuration has changed - the example
config in etc has been modified accordingly.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Philipp Jungkamp
b1e9407f83 packaging-nix: Update inputs
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-26 17:59:39 +02:00
Philipp Jungkamp
33cd6165df Fix fmt 10.0.0 related formatting errors.
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-26 17:59:39 +02:00
Steffen Vogel
926ae841a8 Fix broken include due to auto-formatting
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-08 11:37:42 +02:00
Steffen Vogel
02a2aa4f94 Apply clang-format changes
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-08 11:37:42 +02:00
Philipp Jungkamp
73ca4b5c8d Replace remaining C style comments
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-07 11:16:04 +02:00
bbb3cfe240 Remove more Doxygen-style comments
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-09-07 11:16:04 +02:00
68654f95f2 Add periods after file headers and fix email addresses
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-09-07 11:16:04 +02:00
Steffen Vogel
0735eb0f89 Make project REUSE compliant
And various other cleanups and harmonizations

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-07 11:16:04 +02:00
Steffen Vogel
4b433e20fd Fix include order
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-08-30 13:32:55 +02:00
Steffen Vogel
932ee22472 modbus: Expose socket descriptor to netem emulation
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-08-30 13:32:55 +02:00
Philipp Jungkamp
ad6bd0ecf7 node-file: Don't truncate files
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-25 18:30:27 +02:00
Philipp Jungkamp
2a82e7b388 node-modbus: Improve _read and _write loop
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-23 16:29:53 +02:00
Philipp Jungkamp
a95c4af822 node-modbus: Add details and improve description
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-23 16:29:53 +02:00
Philipp Jungkamp
f229d042d4 node-modbus: Fix code-style
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-23 16:29:53 +02:00
Philipp Jungkamp
5aacd5f49e node-modbus: Add initial modbus support
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-23 16:29:53 +02:00
Niklas Eiling
554515fe30 fix fpga node type to work with current fpga master
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2023-07-25 18:16:51 +02:00
Philipp Jungkamp
d0f1ac749a node-loopback: Fix json_unpack call in parse
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-06-30 18:21:27 +02:00
Philipp Jungkamp
61d5133a40 node-loopback: Fix missing Node::parse call
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-06-30 18:07:32 +02:00
Philipp Jungkamp
82bf4df50c node-webrtc: move peer member initialization to initializer list
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-06-30 14:06:48 +02:00
Steffen Vogel
352c5996db Fix buffer overflow in UUID handling
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 13:26:26 +02:00
Steffen Vogel
50b02df5fd webrtc: Remove unused overload
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 11:53:29 +02:00
Steffen Vogel
82ea02884d webrtc: Show provide status about the RTCPeerConnection via the REST API
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 11:53:29 +02:00
Philipp Jungkamp
f73efabd18 Adapt fpga node to changed uuid passing
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-06-30 11:30:05 +02:00