Pascal Bauer
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a5bb86f39a
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ignore type errors
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
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2024-07-29 14:15:10 +02:00 |
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Pascal Bauer
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64acafa41e
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add module "dinoif_fast_nologic"
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
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2024-07-29 14:15:10 +02:00 |
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Niklas Eiling
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ca03e1d406
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fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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2024-03-14 16:07:45 +01:00 |
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1560f67656
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Reformat Python code with black
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
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2024-02-29 23:18:47 +01:00 |
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a2abaa3cda
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Merge project files, scripts and CMake files of VILLASfpga
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
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2024-02-29 19:33:23 +01:00 |
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3397bca19b
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remove some obsolete scripts
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2018-04-05 10:22:46 +02:00 |
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e0959b562f
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hwdef-parse: parse baseaddr and size of BRAM instances in the design
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2017-11-21 18:42:27 +01:00 |
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5ba80c171d
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hwdef-parse: remove debug output
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2017-11-21 18:42:01 +01:00 |
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502e1f797a
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hwdef-parse: fix errors found by parsing more complex villas hwdef
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2017-11-21 18:41:42 +01:00 |
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857c5c2056
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added hwdef-parse.py
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2017-11-21 18:04:45 +01:00 |
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