a7d24f756f
Remove superfluous includes
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
a5487f4210
test_rtt: Fix cppcheck warnings
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
55238f58b9
test_rtt: Port to C++
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
5ffc0f92f0
test_rtt: Show test process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
d4bc2409c3
Fix some typos and harmonize log output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
3326499e19
Harmonize descriptions of plugins
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
6c5e29de68
webrtc: Fix several TODOs and other smaller tweaks
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
714db711db
Remove unused includes and variables
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
ef27de2d6f
rtp: Fix headers
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
1e6c714560
compat: Update reliability PAI for libdatachannel >= 0.20
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
43a9ab532a
rtp: Upgrade libre dependency to v3.6.0
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
d9b3bdb0de
fpga: DMA: poll BD instead of hardware register
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polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
cc5cd1cbed
fpga: do not create the vfio container twice
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Steffen Vogel
250d016a98
mqtt: Do not attempt validating topics if they are not set
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-06-18 12:39:42 +02:00
dc436073a2
Use spaces for indention of C++ comments
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
4b36073711
Use spaces for indention of CMake files
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
bc670254e2
file: Make directories listable when created
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 22:34:35 +01:00
9247846805
exec: Pass name of node and config path via environment variable to sub-process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-27 19:19:27 +01:00
Niklas Eiling
49523a5076
fpga: remove std::filesystem and properly retrieve searchPath from
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configPath
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
ea0bfcf7f4
fpga: clean up debug outputs
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
26e22ca6f4
fpga: make implementation compatible with new createCard interface
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
47362ccede
fpga: enable inline config of card
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additionally to configuring the card in a separate block, we need to be
able to configure the card from the node config to enable libvillas
users to use the fpga node-type.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Steffen Vogel
226ccecd19
Remove usage of std::filesystem
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-26 17:10:57 +01:00
Steffen Vogel
272a3fac36
Fix include order
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
Steffen Vogel
c1410ef8a8
Fix formatting using clang-format
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
Niklas Eiling
4ca9c88bd0
fpga: add note about wrong cast
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
97a391c271
update fpga submodule
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
18aa0c8862
rework fpga node type
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The various changes in fpga require a rewrite of the fpga node type.
To allow relative paths for the fpga config file, Config and SuperNode
had to be modified so they store the path of the main config file.
The syntax of the fpga node type configuration has changed - the example
config in etc has been modified accordingly.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Philipp Jungkamp
b1e9407f83
packaging-nix: Update inputs
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-26 17:59:39 +02:00
Philipp Jungkamp
33cd6165df
Fix fmt 10.0.0 related formatting errors.
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-26 17:59:39 +02:00
Steffen Vogel
926ae841a8
Fix broken include due to auto-formatting
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-08 11:37:42 +02:00
Steffen Vogel
02a2aa4f94
Apply clang-format changes
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-08 11:37:42 +02:00
Philipp Jungkamp
73ca4b5c8d
Replace remaining C style comments
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-07 11:16:04 +02:00
bbb3cfe240
Remove more Doxygen-style comments
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-09-07 11:16:04 +02:00
68654f95f2
Add periods after file headers and fix email addresses
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-09-07 11:16:04 +02:00
Steffen Vogel
0735eb0f89
Make project REUSE compliant
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And various other cleanups and harmonizations
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-07 11:16:04 +02:00
Steffen Vogel
4b433e20fd
Fix include order
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-08-30 13:32:55 +02:00
Steffen Vogel
932ee22472
modbus: Expose socket descriptor to netem emulation
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-08-30 13:32:55 +02:00
Philipp Jungkamp
ad6bd0ecf7
node-file: Don't truncate files
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-25 18:30:27 +02:00
Philipp Jungkamp
2a82e7b388
node-modbus: Improve _read and _write loop
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-23 16:29:53 +02:00
Philipp Jungkamp
a95c4af822
node-modbus: Add details and improve description
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-23 16:29:53 +02:00
Philipp Jungkamp
f229d042d4
node-modbus: Fix code-style
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-23 16:29:53 +02:00
Philipp Jungkamp
5aacd5f49e
node-modbus: Add initial modbus support
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-08-23 16:29:53 +02:00
Niklas Eiling
554515fe30
fix fpga node type to work with current fpga master
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2023-07-25 18:16:51 +02:00
Philipp Jungkamp
d0f1ac749a
node-loopback: Fix json_unpack call in parse
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-06-30 18:21:27 +02:00
Philipp Jungkamp
61d5133a40
node-loopback: Fix missing Node::parse call
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-06-30 18:07:32 +02:00
Philipp Jungkamp
82bf4df50c
node-webrtc: move peer member initialization to initializer list
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-06-30 14:06:48 +02:00
Steffen Vogel
352c5996db
Fix buffer overflow in UUID handling
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 13:26:26 +02:00
Steffen Vogel
50b02df5fd
webrtc: Remove unused overload
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 11:53:29 +02:00
Steffen Vogel
82ea02884d
webrtc: Show provide status about the RTCPeerConnection via the REST API
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-06-30 11:53:29 +02:00
