1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-09 00:00:00 +01:00
VILLASnode/fpga/lib
Niklas Eiling a000e15308 fpga: make Dino and Aurora IPs optional in utils
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
..
ips fpga: DMA: poll BD instead of hardware register 2024-03-14 16:07:45 +01:00
card.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
CMakeLists.txt Use spaces for indention of CMake files 2024-02-29 23:18:47 +01:00
core.cpp fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs 2024-03-14 16:07:45 +01:00
dma.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
memory.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
node.cpp fix IPs without stream port causing an error and fix formatting in 2024-01-09 17:14:05 +01:00
pcie_card.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
utils.cpp fpga: make Dino and Aurora IPs optional in utils 2024-03-14 16:07:45 +01:00
vlnv.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00