Pascal Bauer cbefe28793 add zynq ip		2024-10-23 22:03:39 +02:00
..
rtds2gpu	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
aurora.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
aurora_xilinx.cpp	Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82)	2023-09-08 11:35:18 +02:00
bram.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
dino.cpp	dino: fix wrong copyright notice in dino.cpp	2024-08-26 10:09:01 +02:00
dma.cpp	fpga: make dma able to handle sequence numbers generated in the FPGA	2024-07-29 13:50:36 +02:00
emc.cpp	Use spaces for indention of C++ comments	2024-02-29 23:18:47 +01:00
fifo.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
gpio.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
i2c.cpp	use polling instead of interrupt	2024-02-26 11:50:44 +01:00
intc.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
pcie.cpp	fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs	2024-03-14 16:07:45 +01:00
register.cpp	fpga: move register config for dino to DinoAdc	2024-05-29 09:18:00 +02:00
rtds.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
switch.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
timer.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
zynq.cpp	add zynq ip	2024-10-23 22:03:39 +02:00