mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-23 00:00:01 +01:00
149 lines
2.8 KiB
Text
149 lines
2.8 KiB
Text
affinity = 0xC;
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debug = 0;
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stats = 1;
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fpga = {
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/* Card identification */
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id = "10ee:7022";
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slot = "01:00.0";
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do_reset = true;
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ips = {
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axi_pcie_intc_0 = {
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vlnv = "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0";
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baseaddr = 0xb000;
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},
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axi_reset_0 = {
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vlnv = "xilinx.com:ip:axi_gpio:2.0";
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baseaddr = 0x7000;
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},
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bram_0 = {
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vlnv = "xilinx.com:ip:axi_bram_ctrl:4.0";
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baseaddr = 0x0000;
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size = 0x2000;
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},
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dma_0 = {
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vlnv = "xilinx.com:ip:axi_dma:7.1";
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baseaddr = 0x3000;
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port = 1;
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irq = 3; /* 3 - 4 */
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},
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timer_0 = {
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vlnv = "xilinx.com:ip:axi_timer:2.0";
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baseaddr = 0x4000;
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irq = 0;
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},
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switch_0 = {
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vlnv = "xilinx.com:ip:axis_interconnect:2.1"
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baseaddr = 0x5000;
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num_ports = 10;
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},
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fifo_mm_s_0 = {
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vlnv = "xilinx.com:ip:axi_fifo_mm_s:4.1";
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baseaddr = 0x6000;
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baseaddr_axi4 = 0xC000;
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port = 2;
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irq = 2;
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},
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rtds_axis_0 = {
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vlnv = "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0";
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baseaddr = 0x8000;
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port = 0;
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irq = 5; /* 5 -7 */
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inputs = {
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in = "axis_interconnect:0"
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},
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outputs = {
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out = "axis_interconnect:0",
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};
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irqs = {
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ts = "axi_pcie_intc_0:5",
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ovfl = "axi_pcie_intc_0:6",
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case = "axi_pcie_intc_0:7",
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}
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},
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dma_1 = {
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vlnv = "xilinx.com:ip:axi_dma:7.1";
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baseaddr = 0x2000;
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port = 6;
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irq = 3; /* 3 - 4 */
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},
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hls_dft_0 = {
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vlnv = "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0";
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baseaddr = 0x9000;
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port = 5;
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irq = 1;
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period = 400; /* in samples: 20ms / 50uS = 400*/
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harmonics = [ 0, 1, 3, 5, 7 ]
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decimation = 1; /* 0 = disabled */
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//harmonics = [ 0, 1, 2, 5, 22 ]
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},
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axis_data_fifo_0 = {
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vlnv = "xilinx.com:ip:axis_data_fifo:1.1";
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port = 3;
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},
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axis_data_fifo_1 = {
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vlnv = "xilinx.com:ip:axis_data_fifo:1.1";
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port = 6;
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},
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}
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/* Configure switch */
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paths = (
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// DM Tests
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// { in = "fifo_mm_s_0", out = "fifo_mm_s_0" },
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// { in = "dma_1", out = "dma_1" },
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// { in = "dma_0", out = "dma_0" }
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// DFT <-> RTDS
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// { in = "rtds_axis_0", out = "hls_dft_0" },
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// { in = "hls_dft_0", out = "rtds_axis_0" }
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// Linux <-> RTDS
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// { in = "rtds_axis_0", out = "dma_1" },
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// { in = "dma_1", out = "rtds_axis_0" }
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// DFT <-> Linux
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{ in = "dma_0", out = "hls_dft_0" },
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{ in = "hls_dft_0", out = "dma_0" }
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)
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}
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plugins = [
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"./lib/cbmodels/simple_circuit.so"
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]
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nodes = {
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dma_0 = {
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type = "fpga";
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datamover = "dma_0";
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},
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dma_1 = {
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type = "fpga";
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datamover = "dma_1";
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},
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fifo_0 = {
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type = "fpga";
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datamover = "fifo_mm_s_0";
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use_irqs = true
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},
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simple_circuit = {
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type = "cbuilder";
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model = "simple_circuit",
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timestep = 25e-6;
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parameters = [
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1.0, /**< R2 = 1 Ohm */
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0.001 /**< C2 = 1000 uF */
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];
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}
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}
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paths = (
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// { in = "dma_1", out = "dma_1" },
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{ in = "dma_1", out = "simple_circuit", reverse = true }
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)
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