mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-23 00:00:01 +01:00

History

Daniel Krebs 89b5169a6e ips/pcie: parse AXI/PCI BARs and create mappings to/from PCIe address space This is used for translations that don't use VFIO which used to bridge the PCIe address space by creating direct mappings from process VA to the FPGA. When we want to communicate directly via PCIe without the involvment of the CPU/VFIO, we need the proper translations that are configured in the FPGA hardware.		2018-05-15 18:04:24 +02:00
..
bitstreams	added fodler for bitstreams	2017-11-21 21:33:19 +01:00
cmake	Squashed 'thirdparty/spdlog/' content from commit 32177aa	2018-01-10 15:24:09 +01:00
doc/pictures	imported source code from VILLASfpga repo and made it compile	2017-11-21 21:31:08 +01:00
etc	config: new config for changed bitstream	2018-05-15 18:04:24 +02:00
include/villas	ips/pcie: parse AXI/PCI BARs and create mappings to/from PCIe address space	2018-05-15 18:04:24 +02:00
lib	ips/pcie: parse AXI/PCI BARs and create mappings to/from PCIe address space	2018-05-15 18:04:24 +02:00
scripts	hwdef-parse: parse PCI and AXI BARs	2018-05-15 18:04:24 +02:00
src	added pkg-config file and CMake configuration for building RPM packages	2018-04-05 11:29:16 +02:00
tests	ips/dma: rename pingpong to memcpy and always connect loopback	2018-05-15 18:04:24 +02:00
thirdparty	common/memory: add host DMA memory allocator using udmabuf	2018-05-15 18:04:24 +02:00
.dockerignore	added simple Dockerfile for development	2017-11-21 21:29:34 +01:00
.editorconfig	imported source code from VILLASfpga repo and made it compile	2017-11-21 21:31:08 +01:00
.gitignore	Squashed 'thirdparty/spdlog/' content from commit 32177aa	2018-01-10 15:24:09 +01:00
.gitlab-ci.yml	do parallel build	2018-01-30 19:36:39 +01:00
.gitmodules	common/memory: add host DMA memory allocator using udmabuf	2018-05-15 18:04:24 +02:00
CHANGELOG.md	created new repo for VILLASfpga	2017-11-21 21:28:21 +01:00
CMakeLists.txt	Merge branch 'develop' into 'feature/packaging'	2018-04-05 11:43:33 +02:00
COPYING.md	created new repo for VILLASfpga	2017-11-21 21:28:21 +01:00
Dockerfile	use official Fedora image as base	2018-01-30 17:55:34 +01:00
libvillas-fpga.pc.in	added pkg-config file and CMake configuration for building RPM packages	2018-04-05 11:29:16 +02:00
README.md	Squashed 'thirdparty/spdlog/' content from commit 32177aa	2018-01-10 15:24:09 +01:00

README.md

VILLASfpga

TODO: Write project description

Documentation

User documentation is available here: https://villas.fein-aachen.org/doc/fpga.html

Copyright

2017, Institute for Automation of Complex Power Systems, EONERC

License

This project is released under the terms of the GPL version 3.

This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.

For other licensing options please consult Prof. Antonello Monti.

Contact

Steffen Vogel stvogel@eonerc.rwth-aachen.de

Institute for Automation of Complex Power Systems (ACS)
EON Energy Research Center (EONERC)
RWTH University Aachen, Germany