1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-30 00:00:11 +01:00
VILLASnode/fpga/lib
Daniel Krebs 89b5169a6e ips/pcie: parse AXI/PCI BARs and create mappings to/from PCIe address space
This is used for translations that don't use VFIO which used to bridge
the PCIe address space by creating direct mappings from process VA to
the FPGA. When we want to communicate directly via PCIe without the
involvment of the CPU/VFIO, we need the proper translations that are
configured in the FPGA hardware.
2018-05-15 18:04:24 +02:00
..
common common/memory: add host DMA memory allocator using udmabuf 2018-05-15 18:04:24 +02:00
gpu gpu: add gdrcopy submodule 2018-05-15 18:04:24 +02:00
ips ips/pcie: parse AXI/PCI BARs and create mappings to/from PCIe address space 2018-05-15 18:04:24 +02:00
kernel kernel/pci: fix unitialized memory 2018-05-15 18:04:24 +02:00
card.cpp fpga/card: make pci device a class member (needed later) 2018-05-15 18:04:24 +02:00
CMakeLists.txt gpu: add empty library for GPU-related stuff 2018-05-15 18:04:24 +02:00
ip.cpp json: parse 64bit numbers, this is required for numbers > 2^31 2018-05-15 18:04:24 +02:00
ip_node.cpp lib/ip: make logger a class member of IpCore 2018-02-14 16:04:33 +01:00
list.c imported source code from VILLASfpga repo and made it compile 2017-11-21 21:31:08 +01:00
log.c make linking of the lib work by using old C-symbols until replaced 2018-01-10 11:02:08 +01:00
log_config.c imported source code from VILLASfpga repo and made it compile 2017-11-21 21:31:08 +01:00
log_helper.c imported source code from VILLASfpga repo and made it compile 2017-11-21 21:31:08 +01:00
utils.c utils: read_random() now returns the number of bytes written 2018-03-26 16:17:26 +02:00
vlnv.cpp lib/vlnv: add != operator and minor cleanup 2018-02-14 07:28:25 +01:00