stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

ZDMA_V1_0: Added ZDMA driver

Browse source 
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
This commit is contained in:
VNSL Durga 2015-03-17 14:11:19 +05:30 • committed by Nava kishore Manne
parent 32c3c2a8bc
commit 08aea016bb
10 changed files with 2997 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

42
XilinxProcessorIPLib/drivers/zdma/data/zdma.mdd Executable file
View file

@ -0,0 +1,42 @@
###############################################################################
#
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
OPTION psf_version = 2.1;
BEGIN driver zdma
OPTION supported_peripherals = (psu_zdma);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = zdma;
END driver

51
XilinxProcessorIPLib/drivers/zdma/data/zdma.tcl Executable file
View file

@ -0,0 +1,51 @@
###############################################################################
#
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
##############################################################################
#
# Modification History
#
# Ver Who Date Changes
# ----- ---- -------- -----------------------------------------------
# 1.0 vnsld 2/24/15 First release
#
##############################################################################
#uses "xillib.tcl"
proc generate {drv_handle} {
::hsi::utils::define_zynq_include_file $drv_handle "xparameters.h" "XZDma" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_DMA_MODE" "C_S_AXI_HIGHADDR" "C_ZDMA_CLK_FREQ_HZ"
::hsi::utils::define_zynq_config_file $drv_handle "xzdma_g.c" "XZDma" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_DMA_MODE"
::hsi::utils::define_zynq_canonical_xpars $drv_handle "xparameters.h" "XZDma" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_DMA_MODE" "C_S_AXI_HIGHADDR" "C_ZDMA_CLK_FREQ_HZ"
}

40
XilinxProcessorIPLib/drivers/zdma/src/Makefile Normal file
View file

@ -0,0 +1,40 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES:=*.c
INCLUDEFILES:=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs: banner zdma_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling zdma"
zdma_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: zdma_includes
zdma_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

1267
XilinxProcessorIPLib/drivers/zdma/src/xzdma.c Normal file
View file

File diff suppressed because it is too large Load diff

667
XilinxProcessorIPLib/drivers/zdma/src/xzdma.h Normal file
View file

@ -0,0 +1,667 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* ZDMA is a general purpose DMA designed to support memory to memory and memory
* to IO buffer transfers. ALTO has two instance of general purpose ZDMA.
* One is located in FPD (full power domain) which is GDMA and other is located
* in LPD (low power domain) which is ADMA.
*
* GMDA & ADMA are configured each with 8 DMA channels and and each channel can
* be programmed secure or non-secure.
* Each channel is divided into two functional sides, Source (Read) and
* Destination (Write). Each DMA channel can be independently programmed
* in one of following DMA modes.
* - Simple DMA
* - Normal data transfer from source to destination.
* - Write Only mode.
* - Read Only mode.
* - Scatter Gather DMA
* - Only Normal mode it can't support other two modes.
* In Scatter gather descriptor can be of 3 types
* - Linear descriptor.
* - Linked list descriptor
* - Hybrid descriptor (Combination of both Linear and Linked list)
* Our driver will not support Hybrid type of descriptor.
*
* <b>Initialization & Configuration</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the ZDMA core.
*
* XZDma_CfgInitialize() API is used to initialize the ZDMA core.
* The user needs to first call the XZDma_LookupConfig() API which returns
* the Configuration structure pointer which is passed as a parameter to the
* XZDma_CfgInitialize() API.
*
* <b> Interrupts </b>
* The driver provides an interrupt handler XZDma_IntrHandler for handling
* the interrupt from the ZDMA core. The users of this driver have to
* register this handler with the interrupt system and provide the callback
* functions by using XZDma_SetCallBack API. In this version Descriptor done
* option is disabled.
*
* <b> Virtual Memory </b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b> Building the driver </b>
*
* The XZDma driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* @file xzdma.h
*
* This header file contains identifiers and register-level driver functions (or
* macros), range macros, structure typedefs that can be used to access the
* Xilinx ZDMA core instance.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vns 2/27/15 First release
* </pre>
*
******************************************************************************/
#ifndef XZDMA_H_
#define XZDMA_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xzdma_hw.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xil_cache.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/** @name ZDMA Handler Types
* @{
*/
typedef enum {
XZDMA_HANDLER_DONE, /**< For Done Handler */
XZDMA_HANDLER_ERROR, /**< For Error Handler */
} XZDma_Handler;
/*@}*/
/** @name ZDMA Descriptors Types
* @{
*/
typedef enum {
XZDMA_LINEAR, /**< Linear descriptor */
XZDMA_LINKEDLIST, /**< Linked list descriptor */
} XZDma_DscrType;
/*@}*/
/** @name ZDMA Operation modes
* @{
*/
typedef enum {
XZDMA_NORMAL_MODE, /**< Normal transfer from source to
* destination*/
XZDMA_WRONLY_MODE, /**< Write only mode */
XZDMA_RDONLY_MODE /**< Read only mode */
} XZDma_Mode;
/*@}*/
/** @name ZDMA state
* @{
*/
typedef enum {
XZDMA_IDLE, /**< ZDMA is in Idle state */
XZDMA_PAUSE, /**< Paused state */
XZDMA_BUSY, /**< Busy state */
} XZDmaState;
/*@}*/
/** @name ZDMA AXI Burst type
* @{
*/
typedef enum {
XZDMA_FIXED_BURST = 0, /**< Fixed burst type */
XZDMA_INCR_BURST /**< Increment burst type */
} XZDma_BurstType;
/*@}*/
/******************************************************************************/
/**
* This typedef contains scatter gather descriptor fields for ZDMA core.
*/
typedef struct {
void *SrcDscrPtr; /**< Source Descriptor pointer */
void *DstDscrPtr; /**< Destination Descriptor pointer */
u32 DscrCount; /**< Count of descriptors available */
XZDma_DscrType DscrType;/**< Type of descriptor either Linear or
* Linked list type */
} XZDma_Descriptor;
/******************************************************************************/
/**
* This typedef contains scatter gather descriptor fields for ZDMA core.
*/
typedef struct {
u64 Address; /**< Address */
u32 Size; /**< Word2, Size of data */
u32 Cntl; /**< Word3 Control data */
u64 NextDscr; /**< Address of next descriptor */
u64 Reserved; /**< Reserved address */
} __attribute__ ((packed)) XZDma_LlDscr;
/******************************************************************************/
/**
* This typedef contains Linear descriptor fields for ZDMA core.
*/
typedef struct {
u64 Address; /**< Address */
u32 Size; /**< Word3, Size of data */
u32 Cntl; /**< Word4, control data */
} __attribute__ ((packed)) XZDma_LiDscr;
/******************************************************************************/
/**
*
* This typedef contains the data configurations of ZDMA core
*/
typedef struct {
u8 OverFetch; /**< Enable Over fetch */
u8 SrcIssue; /**< Outstanding transactions for Source */
XZDma_BurstType SrcBurstType;
/**< Burst type for SRC */
u8 SrcBurstLen; /**< AXI length for data read */
XZDma_BurstType DstBurstType;
/**< Burst type for DST */
u8 DstBurstLen; /**< AXI length for data write */
u8 SrcCache; /**< AXI cache bits for data read */
u8 SrcQos; /**< AXI QOS bits for data read */
u8 DstCache; /**< AXI cache bits for data write */
u8 DstQos; /**< AXI QOS bits for data write */
} XZDma_DataConfig;
/******************************************************************************/
/**
*
* This typedef contains the descriptor configurations of ZDMA core
*/
typedef struct{
u8 AxCoherent; /**< AXI transactions are coherent or non-coherent */
u8 AXCache; /**< AXI cache for DSCR fetch */
u8 AXQos; /**< Qos bit for DSCR fetch */
} XZDma_DscrConfig;
/******************************************************************************/
/**
* Callback type for Completion of all data transfers.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
*******************************************************************************/
typedef void (*XZDma_DoneHandler) (void *CallBackRef);
/******************************************************************************/
/**
* Callback type for all error interrupts.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
* @param ErrorMask is a bit mask indicating the cause of the error. Its
* value equals 'OR'ing one or more XZDMA_IXR_* values defined in
* xzdma_hw.h
****************************************************************************/
typedef void (*XZDma_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
/**
* This typedef contains configuration information for a ZDMA core
* Each ZDMA core should have a configuration structure associated.
*/
typedef struct {
u16 DeviceId; /**< Device Id of ZDMA */
u32 BaseAddress; /**< BaseAddress of ZDMA */
u8 DmaType; /**< Type of DMA */
} XZDma_Config;
/******************************************************************************/
/**
*
* The XZDma driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
XZDma_Config Config; /**< Hardware configuration */
u32 IsReady; /**< Device and the driver instance
* are initialized */
u32 IntrMask; /**< Mask for enabling interrupts */
XZDma_Mode Mode; /**< Mode of ZDMA core to be operated */
u8 IsSgDma; /**< Is ZDMA core is in scatter gather or
* not will be specified */
XZDma_Descriptor Descriptor; /**< It contains information about
* descriptors */
XZDma_DoneHandler DoneHandler; /**< Call back for transfer
* done interrupt */
void *DoneRef; /**< To be passed to the done
* interrupt callback */
XZDma_ErrorHandler ErrorHandler;/**< Call back for error
* interrupt */
void *ErrorRef; /**< To be passed to the error
* interrupt callback */
XZDma_DataConfig DataConfig; /**< Current configurations */
XZDma_DscrConfig DscrConfig; /**< Current configurations */
XZDmaState ChannelState; /**< ZDMA channel is busy */
} XZDma;
/******************************************************************************/
/**
*
* This typedef contains the fields for transfer of data.
*/
typedef struct {
UINTPTR SrcAddr; /**< Source address */
UINTPTR DstAddr; /**< Destination Address */
u32 Size; /**< Size of the data to be transferred */
u8 SrcCoherent; /**< Source coherent */
u8 DstCoherent; /**< Destination coherent */
u8 Pause; /**< Will pause data transmission after
* this transfer only for SG mode */
} XZDma_Transfer;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* This function returns interrupt status read from Interrupt Status Register.
* Use the XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to interpret the
* returned value.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return The pending interrupts of the ZDMA core.
* Use the masks specified in xzdma_hw.h to interpret
* the returned value.
* @note
* C-style signature:
* void XZDma_IntrGetStatus(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_IntrGetStatus(InstancePtr) \
XZDma_ReadReg((InstancePtr)->Config.BaseAddress, XZDMA_CH_ISR_OFFSET)
/*****************************************************************************/
/**
*
* This function clears interrupt(s). Every bit set in Interrupt Status
* Register indicates that a specific type of interrupt is occurring, and this
* function clears one or more interrupts by writing a bit mask to Interrupt
* Clear Register.
*
* @param InstancePtr is a pointer to the XZDma instance.
* @param Mask is the type of the interrupts to enable. Use OR'ing of
* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
* this parameter value.
*
* @return None.
*
* @note
* C-style signature:
* void XZDma_IntrClear(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_IntrClear(InstancePtr, Mask) \
XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
XZDMA_CH_ISR_OFFSET, ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK))
/*****************************************************************************/
/**
*
* This function returns interrupt mask to know which interrupts are
* enabled and which of them were disabled.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return The current interrupt mask. The mask indicates which interrupts
* are enabled/disabled.
* 0 bit represents .....corresponding interrupt is enabled.
* 1 bit represents .....Corresponding interrupt is disabled.
*
* @note
* C-style signature:
* void XZDma_GetIntrMask(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_GetIntrMask(InstancePtr) \
XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
(u32)(XZDMA_CH_IMR_OFFSET))
/*****************************************************************************/
/**
*
* This function enables individual interrupts of the ZDMA core by updating
* the Interrupt Enable register.
*
* @param InstancePtr is a pointer to the XZDma instance.
* @param Mask is the type of the interrupts to enable. Use OR'ing of
* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
* this parameter value.
*
* @return None.
*
* @note The existing enabled interrupt(s) will remain enabled.
* C-style signature:
* void XZDma_EnableIntr(XZDma *InstancePtr, u32 Mask)
*
******************************************************************************/
#define XZDma_EnableIntr(InstancePtr, Mask) \
(InstancePtr)->IntrMask = ((InstancePtr)->IntrMask | (Mask))
/*****************************************************************************/
/**
*
* This function disables individual interrupts of the ZDMA core by updating
* the Interrupt Disable register.
*
* @param InstancePtr is a pointer to the XZDma instance.
* @param Mask is the type of the interrupts to disable. Use OR'ing of
* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
* this parameter value.
*
* @return None.
*
* @note The existing disabled interrupt(s) will remain disabled.
* C-style signature:
* void XZDma_DisableIntr(XZDma *InstancePtr, u32 Mask)
*
******************************************************************************/
#define XZDma_DisableIntr(InstancePtr, Mask) \
XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
XZDMA_CH_IDS_OFFSET, \
((u32)XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_IDS_OFFSET) | ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK)))
/*****************************************************************************/
/**
*
* This function returns source current payload address under process
* of ZDMA core.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note This address may not be precise due to ZDMA pipeline structure
* C-style signature:
* u64 XZDma_SrcCurPyld(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_SrcCurPyld(InstancePtr) \
((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET)) | \
((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
/*****************************************************************************/
/**
*
* This function returns destination current payload address under process
* of ZDMA core.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note This address may not be precise due to ZDMA pipeline structure
* C-style signature:
* u64 XZDma_DstCurPyld(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_DstCurPyld(InstancePtr) \
((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET)) | \
((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
/*****************************************************************************/
/**
*
* This function returns source descriptor current payload address under
* process of ZDMA core.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note This address may not be precise due to ZDMA pipeline structure
* C-style signature:
* u64 XZDma_SrcDscrCurPyld(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_SrcDscrCurPyld(InstancePtr) \
((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET)) | \
((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
/*****************************************************************************/
/**
*
* This function returns destination descriptor current payload address under
* process of ZDMA core.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note This address may not be precise due to ZDMA pipeline structure
* C-style signature:
* u64 XZDma_DstDscrCurPyld(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_DstDscrCurPyld(InstancePtr) \
((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET)) | \
((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
/*****************************************************************************/
/**
*
* This function gets the count of total bytes transferred through core
* since last clear in ZDMA core.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note
* C-style signature:
* void XZDma_GetTotalByte(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_GetTotalByte(InstancePtr) \
XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_TOTAL_BYTE_OFFSET)
/*****************************************************************************/
/**
*
* This function clears the count of total bytes transferred in ZDMA core.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note
* C-style signature:
* void XZDma_TotalByteClear(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_TotalByteClear(InstancePtr) \
XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
(XZDMA_CH_TOTAL_BYTE_OFFSET), (XZDMA_WRITE_TO_CLEAR_MASK))
/*****************************************************************************/
/**
*
* This function gets the total number of Interrupt count for source after last
* call of this API.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note Once this API is called then count will become zero.
* C-style signature:
* void XZDma_GetSrcIntrCnt(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_GetSrcIntrCnt(InstancePtr) \
XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_IRQ_SRC_ACCT_OFFSET)
/*****************************************************************************/
/**
*
* This function gets the total number of Interrupt count for destination
* after last call of this API.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note Once this API is called then count will become zero.
* C-style signature:
* void XZDma_GetDstIntrCnt(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_GetDstIntrCnt(InstancePtr) \
XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
XZDMA_CH_IRQ_DST_ACCT_OFFSET)
/*****************************************************************************/
/**
*
* This function Enable's the ZDMA core for initiating the data transfer once the
* data transfer completes it will be automatically disabled.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note None.
* C-style signature:
* void XZDma_EnableCh(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_EnableCh(InstancePtr) \
XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
(XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_EN_MASK))
/*****************************************************************************/
/**
*
* This function Disable's the ZDMA core.
*
* @param InstancePtr is a pointer to the XZDma instance.
*
* @return None.
*
* @note None.
* C-style signature:
* void XZDma_DisableCh(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_DisableCh(InstancePtr) \
XZDma_WriteReg((InstancePtr)->Config.BaseAddress,\
(XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_DIS_MASK))
/************************ Prototypes of functions **************************/
XZDma_Config *XZDma_LookupConfig(u16 DeviceId);
s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr,
u32 EffectiveAddr);
s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode);
u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr,
UINTPTR Dscr_MemPtr, u32 NoOfBytes);
s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num);
void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer);
void XZDma_Resume(XZDma *InstancePtr);
void XZDma_Reset(XZDma *InstancePtr);
XZDmaState XZDma_ChannelState(XZDma *InstancePtr);
s32 XZDma_SelfTest(XZDma *InstancePtr);
void XZDma_IntrHandler(void *Instance);
s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
void *CallBackFunc, void *CallBackRef);
/*@}*/
#ifdef __cplusplus
}
#endif
#endif /* XZDMA_H_ */

129
XilinxProcessorIPLib/drivers/zdma/src/xzdma_g.c Normal file
View file

@ -0,0 +1,129 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xzdma.h"
/*
* The configuration table for devices
*/
XZDma_Config XZDma_ConfigTable[] =
{
{
XPAR_PSU_ADMA_CH0_DEVICE_ID,
XPAR_PSU_ADMA_CH0_BASEADDR,
XPAR_PSU_ADMA_CH0_DMA_MODE
},
{
XPAR_PSU_ADMA_CH1_DEVICE_ID,
XPAR_PSU_ADMA_CH1_BASEADDR,
XPAR_PSU_ADMA_CH1_DMA_MODE
},
{
XPAR_PSU_ADMA_CH2_DEVICE_ID,
XPAR_PSU_ADMA_CH2_BASEADDR,
XPAR_PSU_ADMA_CH2_DMA_MODE
},
{
XPAR_PSU_ADMA_CH3_DEVICE_ID,
XPAR_PSU_ADMA_CH3_BASEADDR,
XPAR_PSU_ADMA_CH3_DMA_MODE
},
{
XPAR_PSU_ADMA_CH4_DEVICE_ID,
XPAR_PSU_ADMA_CH4_BASEADDR,
XPAR_PSU_ADMA_CH4_DMA_MODE
},
{
XPAR_PSU_ADMA_CH5_DEVICE_ID,
XPAR_PSU_ADMA_CH5_BASEADDR,
XPAR_PSU_ADMA_CH5_DMA_MODE
},
{
XPAR_PSU_ADMA_CH6_DEVICE_ID,
XPAR_PSU_ADMA_CH6_BASEADDR,
XPAR_PSU_ADMA_CH6_DMA_MODE
},
{
XPAR_PSU_ADMA_CH7_DEVICE_ID,
XPAR_PSU_ADMA_CH7_BASEADDR,
XPAR_PSU_ADMA_CH7_DMA_MODE
},
{
XPAR_PSU_GDMA_CH0_DEVICE_ID,
XPAR_PSU_GDMA_CH0_BASEADDR,
XPAR_PSU_GDMA_CH0_DMA_MODE
},
{
XPAR_PSU_GDMA_CH1_DEVICE_ID,
XPAR_PSU_GDMA_CH1_BASEADDR,
XPAR_PSU_GDMA_CH1_DMA_MODE
},
{
XPAR_PSU_GDMA_CH2_DEVICE_ID,
XPAR_PSU_GDMA_CH2_BASEADDR,
XPAR_PSU_GDMA_CH2_DMA_MODE
},
{
XPAR_PSU_GDMA_CH3_DEVICE_ID,
XPAR_PSU_GDMA_CH3_BASEADDR,
XPAR_PSU_GDMA_CH3_DMA_MODE
},
{
XPAR_PSU_GDMA_CH4_DEVICE_ID,
XPAR_PSU_GDMA_CH4_BASEADDR,
XPAR_PSU_GDMA_CH4_DMA_MODE
},
{
XPAR_PSU_GDMA_CH5_DEVICE_ID,
XPAR_PSU_GDMA_CH5_BASEADDR,
XPAR_PSU_GDMA_CH5_DMA_MODE
},
{
XPAR_PSU_GDMA_CH6_DEVICE_ID,
XPAR_PSU_GDMA_CH6_BASEADDR,
XPAR_PSU_GDMA_CH6_DMA_MODE
},
{
XPAR_PSU_GDMA_CH7_DEVICE_ID,
XPAR_PSU_GDMA_CH7_BASEADDR,
XPAR_PSU_GDMA_CH7_DMA_MODE
}
};

380
XilinxProcessorIPLib/drivers/zdma/src/xzdma_hw.h Normal file
View file

@ -0,0 +1,380 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xzdma_hw.h
*
* This header file contains identifiers and register-level driver functions (or
* macros) that can be used to access the Xilinx ZDMA core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vns 2/27/15 First release
* </pre>
*
******************************************************************************/
#ifndef XZDMA_HW_H_
#define XZDMA_HW_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers offsets
* @{
*/
#define XZDMA_ERR_CTRL (0x000U)
#define XZDMA_CH_ECO (0x004U)
#define XZDMA_CH_ISR_OFFSET (0x100U)
#define XZDMA_CH_IMR_OFFSET (0x104U)
#define XZDMA_CH_IEN_OFFSET (0x108U)
#define XZDMA_CH_IDS_OFFSET (0x10CU)
#define XZDMA_CH_CTRL0_OFFSET (0x110U)
#define XZDMA_CH_CTRL1_OFFSET (0x114U)
#define XZDMA_CH_PERIF_OFFSET (0x118U)
#define XZDMA_CH_STS_OFFSET (0x11CU)
#define XZDMA_CH_DATA_ATTR_OFFSET (0x120U)
#define XZDMA_CH_DSCR_ATTR_OFFSET (0x124U)
#define XZDMA_CH_SRC_DSCR_WORD0_OFFSET (0x128U)
#define XZDMA_CH_SRC_DSCR_WORD1_OFFSET (0x12CU)
#define XZDMA_CH_SRC_DSCR_WORD2_OFFSET (0x130U)
#define XZDMA_CH_SRC_DSCR_WORD3_OFFSET (0x134U)
#define XZDMA_CH_DST_DSCR_WORD0_OFFSET (0x138U)
#define XZDMA_CH_DST_DSCR_WORD1_OFFSET (0x13CU)
#define XZDMA_CH_DST_DSCR_WORD2_OFFSET (0x140U)
#define XZDMA_CH_DST_DSCR_WORD3_OFFSET (0x144U)
#define XZDMA_CH_WR_ONLY_WORD0_OFFSET (0x148U)
#define XZDMA_CH_WR_ONLY_WORD1_OFFSET (0x14CU)
#define XZDMA_CH_WR_ONLY_WORD2_OFFSET (0x150U)
#define XZDMA_CH_WR_ONLY_WORD3_OFFSET (0x154U)
#define XZDMA_CH_SRC_START_LSB_OFFSET (0x158U)
#define XZDMA_CH_SRC_START_MSB_OFFSET (0x15CU)
#define XZDMA_CH_DST_START_LSB_OFFSET (0x160U)
#define XZDMA_CH_DST_START_MSB_OFFSET (0x164U)
#define XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET (0x168U)
#define XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET (0x16CU)
#define XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET (0x170U)
#define XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET (0x174U)
#define XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET (0x178U)
#define XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET (0x17CU)
#define XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET (0x180U)
#define XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET (0x184U)
#define XZDMA_CH_TOTAL_BYTE_OFFSET (0x188U)
#define XZDMA_CH_RATE_CNTL_OFFSET (0x18CU)
#define XZDMA_CH_IRQ_SRC_ACCT_OFFSET (0x190U)
#define XZDMA_CH_IRQ_DST_ACCT_OFFSET (0x194U)
#define XZDMA_CH_CTRL2_OFFSET (0x200U)
/*@}*/
/** @name Interrupt Enable/Disable/Mask/Status registers bit masks and shifts
* @{
*/
#define XZDMA_IXR_DMA_PAUSE_MASK (0x00000800U) /**< IXR pause mask */
#define XZDMA_IXR_DMA_DONE_MASK (0x00000400U) /**< IXR done mask */
#define XZDMA_IXR_AXI_WR_DATA_MASK (0x00000200U) /**< IXR AXI write data
* error mask */
#define XZDMA_IXR_AXI_RD_DATA_MASK (0x00000100U) /**< IXR AXI read data
* error mask */
#define XZDMA_IXR_AXI_RD_DST_DSCR_MASK (0x00000080U) /**< IXR AXI read
* descriptor error
* mask */
#define XZDMA_IXR_AXI_RD_SRC_DSCR_MASK (0x00000040U) /**< IXR AXI write
* descriptor error
* mask */
#define XZDMA_IXR_DST_ACCT_ERR_MASK (0x00000020U) /**< IXR DST interrupt
* count overflow
* mask */
#define XZDMA_IXR_SRC_ACCT_ERR_MASK (0x00000010U) /**< IXR SRC interrupt
* count overflow
* mask */
#define XZDMA_IXR_BYTE_CNT_OVRFL_MASK (0x00000008U) /**< IXR byte count over
* flow mask */
#define XZDMA_IXR_DST_DSCR_DONE_MASK (0x00000004U) /**< IXR destination
* descriptor done
* mask */
#define XZDMA_IXR_SRC_DSCR_DONE_MASK (0x00000002U) /**< IXR source
* descriptor done
* mask */
#define XZDMA_IXR_INV_APB_MASK (0x00000001U) /**< IXR invalid APB
* access mask */
#define XZDMA_IXR_ALL_INTR_MASK (0x00000FFFU) /**< IXR OR of all the
* interrupts mask */
#define XZDMA_IXR_DONE_MASK (0x00000400U) /**< IXR All done mask */
#define XZDMA_IXR_ERR_MASK (0x00000BF9U) /**< IXR all Error mask*/
/**< Or of XZDMA_IXR_AXI_WR_DATA_MASK,
* XZDMA_IXR_AXI_RD_DATA_MASK,
* XZDMA_IXR_AXI_RD_DST_DSCR_MASK,
* XZDMA_IXR_AXI_RD_SRC_DSCR_MASK,
* XZDMA_IXR_INV_APB_MASK,
* XZDMA_IXR_DMA_PAUSE_MASK,
* XZDMA_IXR_BYTE_CNT_OVRFL_MASK,
* XZDMA_IXR_SRC_ACCT_ERR_MASK,
* XZDMA_IXR_DST_ACCT_ERR_MASK */
/*@}*/
/** @name Channel Control0 register bit masks and shifts
* @{
*/
#define XZDMA_CTRL0_OVR_FETCH_MASK (0x00000080U) /**< Over fetch mask */
#define XZDMA_CTRL0_POINT_TYPE_MASK (0x00000040U) /**< Pointer type mask */
#define XZDMA_CTRL0_MODE_MASK (0x00000030U) /**< Mode mask */
#define XZDMA_CTRL0_WRONLY_MASK (0x00000010U) /**< Write only mask */
#define XZDMA_CTRL0_RDONLY_MASK (0x00000020U) /**< Read only mask */
#define XZDMA_CTRL0_RATE_CNTL_MASK (0x00000008U) /**< Rate control mask */
#define XZDMA_CTRL0_CONT_ADDR_MASK (0x00000004U) /**< Continue address
* specified mask */
#define XZDMA_CTRL0_CONT_MASK (0x00000002U) /**< Continue mask */
#define XZDMA_CTRL0_OVR_FETCH_SHIFT (7U) /**< Over fetch shift */
#define XZDMA_CTRL0_POINT_TYPE_SHIFT (6U) /**< Pointer type shift */
#define XZDMA_CTRL0_MODE_SHIFT (4U) /**< Mode type shift */
#define XZDMA_CTRL0_RESET_VALUE (0x00000080U) /**< CTRL0 reset value */
/*@}*/
/** @name Channel Control1 register bit masks and shifts
* @{
*/
#define XZDMA_CTRL1_SRC_ISSUE_MASK (0x0000001FU) /**< Source issue mask */
#define XZDMA_CTRL1_RESET_VALUE (0x000003FFU) /**< CTRL1 reset value */
/*@}*/
/** @name Channel Peripheral register bit masks and shifts
* @{
*/
#define XZDMA_PERIF_PROG_CELL_CNT_MASK (0x0000003EU) /**< Peripheral program
* cell count */
#define XZDMA_PERIF_SIDE_MASK (0x00000002U) /**< Interface attached
* the side mask */
#define XZDMA_PERIF_EN_MASK (0x00000001U) /**< Peripheral flow
* control mask */
/*@}*/
/** @name Channel Status register bit masks and shifts
* @{
*/
#define XZDMA_STS_DONE_ERR_MASK (0x00000003U) /**< Done with errors mask */
#define XZDMA_STS_BUSY_MASK (0x00000002U) /**< ZDMA is busy in transfer
* mask */
#define XZDMA_STS_PAUSE_MASK (0x00000001U) /**< ZDMA is in Pause state
* mask */
#define XZDMA_STS_DONE_MASK (0x00000000U) /**< ZDMA done mask */
#define XZDMA_STS_ALL_MASK (0x00000003U) /**< ZDMA status mask */
/*@}*/
/** @name Channel Data Attribute register bit masks and shifts
* @{
*/
#define XZDMA_DATA_ATTR_ARBURST_MASK (0x0C000000U) /**< Data ArBurst mask */
#define XZDMA_DATA_ATTR_ARCACHE_MASK (0x03C00000U) /**< Data ArCache mask */
#define XZDMA_DATA_ATTR_ARQOS_MASK (0x003C0000U) /**< Data ARQos masks */
#define XZDMA_DATA_ATTR_ARLEN_MASK (0x0003C000U) /**< Data Arlen mask */
#define XZDMA_DATA_ATTR_AWBURST_MASK (0x00003000U) /**< Data Awburst mask */
#define XZDMA_DATA_ATTR_AWCACHE_MASK (0x00000F00U) /**< Data AwCache mask */
#define XZDMA_DATA_ATTR_AWQOS_MASK (0x000000F0U) /**< Data AwQos mask */
#define XZDMA_DATA_ATTR_AWLEN_MASK (0x0000000FU) /**< Data Awlen mask */
#define XZDMA_DATA_ATTR_ARBURST_SHIFT (26U) /**< Data Arburst shift */
#define XZDMA_DATA_ATTR_ARCACHE_SHIFT (22U) /**< Data ArCache shift */
#define XZDMA_DATA_ATTR_ARQOS_SHIFT (18U) /**< Data ARQos shift */
#define XZDMA_DATA_ATTR_ARLEN_SHIFT (14U) /**< Data Arlen shift */
#define XZDMA_DATA_ATTR_AWBURST_SHIFT (12U) /**< Data Awburst shift */
#define XZDMA_DATA_ATTR_AWCACHE_SHIFT (8U) /**< Data Awcache shift */
#define XZDMA_DATA_ATTR_AWQOS_SHIFT (4U) /**< Data Awqos shift */
#define XZDMA_DATA_ATTR_RESET_VALUE (0x0483D20FU) /**< Data Attributes
* reset value */
/*@}*/
/** @name Channel DSCR Attribute register bit masks and shifts
* @{
*/
#define XZDMA_DSCR_ATTR_AXCOHRNT_MASK (0x00000100U) /**< Descriptor coherent
* mask */
#define XZDMA_DSCR_ATTR_AXCACHE_MASK (0x000000F0U) /**< Descriptor cache
* mask */
#define XZDMA_DSCR_ATTR_AXQOS_MASK (0x0000000FU) /**< Descriptor AxQos
* mask */
#define XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT (8U) /**< Descriptor coherent shift */
#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT (7U) /**< Descriptor cache shift */
#define XZDMA_DSCR_ATTR_RESET_VALUE (0x00000000U) /**< Dscr Attributes
* reset value */
/*@}*/
/** @name Channel Source/Destination Word0 register bit mask
* @{
*/
#define XZDMA_WORD0_LSB_MASK (0xFFFFFFFFU) /**< LSB Address mask */
/*@}*/
/** @name Channel Source/Destination Word1 register bit mask
* @{
*/
#define XZDMA_WORD1_MSB_MASK (0x0001FFFFU) /**< MSB Address mask */
#define XZDMA_WORD1_MSB_SHIFT (32U) /**< MSB Address shift */
/*@}*/
/** @name Channel Source/Destination Word2 register bit mask
* @{
*/
#define XZDMA_WORD2_SIZE_MASK (0x3FFFFFFFU) /**< Size mask */
/*@}*/
/** @name Channel Source/Destination Word3 register bit masks and shifts
* @{
*/
#define XZDMA_WORD3_CMD_MASK (0x00000018U) /**< Cmd mask */
#define XZDMA_WORD3_CMD_SHIFT (3U) /**< Cmd shift */
#define XZDMA_WORD3_CMD_NXTVALID_MASK (0x00000000U) /**< Next Dscr is valid
* mask */
#define XZDMA_WORD3_CMD_PAUSE_MASK (0x00000008U) /**< Pause after this
* dscr mask */
#define XZDMA_WORD3_CMD_STOP_MASK (0x00000010U) /**< Stop after this
..* dscr mask */
#define XZDMA_WORD3_INTR_MASK (0x00000004U) /**< Interrupt
* enable or disable
* mask */
#define XZDMA_WORD3_INTR_SHIFT (2U) /**< Interrupt enable
* disable
* shift */
#define XZDMA_WORD3_TYPE_MASK (0x00000002U) /**< Type of Descriptor
* mask */
#define XZDMA_WORD3_TYPE_SHIFT (1U) /**< Type of Descriptor
* Shift */
#define XZDMA_WORD3_COHRNT_MASK (0x00000001U) /**< Coherence mask */
/*@}*/
/** @name Channel Source/Destination start address or current payload
* MSB register bit mask
* @{
*/
#define XZDMA_START_MSB_ADDR_MASK (0x0001FFFFU) /**< Start msb address
* mask */
/*@}*/
/** @name Channel Rate control count register bit mask
* @{
*/
#define XZDMA_CH_RATE_CNTL_MASK (0x00000FFFU) /**< Channel rate control
* mask */
/*@}*/
/** @name Channel Source/Destination Interrupt account count register bit mask
* @{
*/
#define XZDMA_CH_IRQ_ACCT_MASK (0x000000FFU) /**< Interrupt count
* mask */
/*@}*/
/** @name Channel debug register 0/1 bit mask
* @{
*/
#define XZDMA_CH_DBG_CMN_BUF_MASK (0x000001FFU) /**< Common buffer count
* mask */
/*@}*/
/** @name Channel control2 register bit mask
* @{
*/
#define XZDMA_CH_CTRL2_EN_MASK (0x00000001U) /**< Channel enable
* mask */
#define XZDMA_CH_CTRL2_DIS_MASK (0x00000000U) /**< Channel disable
* mask */
/*@}*/
/** @name Channel control2 register bit mask
* @{
*/
#define XZDMA_WRITE_TO_CLEAR_MASK (0x00000000U) /**< Write to clear
* mask */
/*@}*/
/***************** Macros (Inline Functions) Definitions *********************/
#define XZDma_In32 Xil_In32 /**< Input operation */
#define XZDma_Out32 Xil_Out32 /**< Output operation */
/*****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddress is the Xilinx base address of the ZDMA core.
* @param RegOffset is the register offset of the register.
*
* @return The 32-bit value of the register.
*
* @note C-style signature:
* u32 XZDma_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XZDma_ReadReg(BaseAddress, RegOffset) \
XZDma_In32((BaseAddress) + (u32)(RegOffset))
/*****************************************************************************/
/**
*
* This macro writes the value into the given register.
*
* @param BaseAddress is the Xilinx base address of the ZDMA core.
* @param RegOffset is the register offset of the register.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note C-style signature:
* void XZDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XZDma_WriteReg(BaseAddress, RegOffset, Data) \
XZDma_Out32(((BaseAddress) + (u32)(RegOffset)), (u32)(Data))
#ifdef __cplusplus
}
#endif
#endif /* XZDMA_HW_H_ */

202
XilinxProcessorIPLib/drivers/zdma/src/xzdma_intr.c Normal file
View file

@ -0,0 +1,202 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xzdma_intr.c
*
* This file contains interrupt related functions of Xilinx ZDMA core.
* Please see xzdma.h for more details of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vns 2/27/15 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xzdma.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function is the interrupt handler for the ZDMA core.
*
* This handler reads the pending interrupt from Status register, determines the
* source of the interrupts and calls the respective callbacks for the
* interrupts that are enabled in IRQ_ENABLE register, and finally clears the
* interrupts.
*
* The application is responsible for connecting this function to the interrupt
* system. Application beyond this driver is also responsible for providing
* callbacks to handle interrupts and installing the callbacks using
* XZDma_SetCallBack() during initialization phase. .
*
* @param Instance is a pointer to the XZDma instance to be worked on.
*
* @return None.
*
* @note To generate interrupt required interrupts should be enabled.
*
******************************************************************************/
void XZDma_IntrHandler(void *Instance)
{
u32 PendingIntr;
u32 ErrorStatus;
XZDma *InstancePtr = NULL;
InstancePtr = (XZDma *)((void *)Instance);
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
/* Get pending interrupts */
PendingIntr = (u32)(XZDma_IntrGetStatus(InstancePtr));
PendingIntr &= (~XZDma_GetIntrMask(InstancePtr));
/* ZDMA transfer has completed */
ErrorStatus = (PendingIntr) & (XZDMA_IXR_DMA_DONE_MASK);
if ((ErrorStatus) != 0U) {
XZDma_DisableIntr(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
InstancePtr->ChannelState = XZDMA_IDLE;
InstancePtr->DoneHandler(InstancePtr->DoneRef);
}
/* An error has been occurred */
ErrorStatus = PendingIntr & (XZDMA_IXR_ERR_MASK);
if ((ErrorStatus) != 0U) {
if ((ErrorStatus & XZDMA_IXR_DMA_PAUSE_MASK) ==
XZDMA_IXR_DMA_PAUSE_MASK) {
InstancePtr->ChannelState = XZDMA_PAUSE;
}
else {
if ((ErrorStatus & (XZDMA_IXR_AXI_WR_DATA_MASK |
XZDMA_IXR_AXI_RD_DATA_MASK |
XZDMA_IXR_AXI_RD_DST_DSCR_MASK |
XZDMA_IXR_AXI_RD_SRC_DSCR_MASK)) != 0x00U) {
InstancePtr->ChannelState = XZDMA_IDLE;
}
}
InstancePtr->ErrorHandler(InstancePtr->ErrorRef, ErrorStatus);
}
/* Clear pending interrupt(s) */
XZDma_IntrClear(InstancePtr, PendingIntr);
}
/*****************************************************************************/
/**
*
* This routine installs an asynchronous callback function for the given
* HandlerType.
*
* <pre>
* HandlerType Callback Function Type
* ----------------------- --------------------------------------------------
* XZDMA_HANDLER_DONE Done handler
* XZDMA_HANDLER_ERROR Error handler
*
* </pre>
*
* @param InstancePtr is a pointer to the XZDma instance to be worked on.
* @param HandlerType specifies which callback is to be attached.
* @param CallBackFunc is the address of the callback function.
* @param CallBackRef is a user data item that will be passed to the
* callback function when it is invoked.
*
* @return
* - XST_SUCCESS when handler is installed.
* - XST_INVALID_PARAM when HandlerType is invalid.
*
* @note Invoking this function for a handler that already has been
* installed replaces it with the new handler.
*
******************************************************************************/
s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
void *CallBackFunc, void *CallBackRef)
{
s32 Status;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CallBackFunc != NULL);
Xil_AssertNonvoid(CallBackRef != NULL);
Xil_AssertNonvoid((HandlerType == XZDMA_HANDLER_DONE) ||
(HandlerType == XZDMA_HANDLER_ERROR));
Xil_AssertNonvoid(InstancePtr->IsReady ==
(u32)(XIL_COMPONENT_IS_READY));
/*
* Calls the respective callback function corresponding to
* the handler type
*/
switch (HandlerType) {
case XZDMA_HANDLER_DONE:
InstancePtr->DoneHandler =
(XZDma_DoneHandler)((void *)CallBackFunc);
InstancePtr->DoneRef = CallBackRef;
Status = (XST_SUCCESS);
break;
case XZDMA_HANDLER_ERROR:
InstancePtr->ErrorHandler =
(XZDma_ErrorHandler)((void *)CallBackFunc);
InstancePtr->ErrorRef = CallBackRef;
Status = (XST_SUCCESS);
break;
default:
Status = (XST_INVALID_PARAM);
break;
}
return Status;
}

116
XilinxProcessorIPLib/drivers/zdma/src/xzdma_selftest.c Normal file
View file

@ -0,0 +1,116 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xzdma_selftest.c
*
* This file contains the self-test function for the ZDMA core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vns 2/27/15 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xzdma.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This file contains a diagnostic self-test function for the ZDMA driver.
* Refer to the header file xzdma.h for more detailed information.
*
* @param InstancePtr is a pointer to XZDma instance.
*
* @return
* - XST_SUCCESS if the test is successful.
* - XST_FAILURE if the test is failed.
*
* @note None.
*
******************************************************************************/
s32 XZDma_SelfTest(XZDma *InstancePtr)
{
u32 Data;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
XZDMA_CH_CTRL0_OFFSET);
/* Changing DMA channel to over fetch */
XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
(Data | XZDMA_CTRL0_OVR_FETCH_MASK));
if (((u32)XZDma_ReadReg(InstancePtr->Config.BaseAddress,
XZDMA_CH_CTRL0_OFFSET) & XZDMA_CTRL0_OVR_FETCH_MASK) !=
XZDMA_CTRL0_OVR_FETCH_MASK) {
Status = (s32)XST_FAILURE;
}
else {
Status = (s32)XST_SUCCESS;
}
/* Retrieving the change settings */
XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
Data);
return Status;
}

103
XilinxProcessorIPLib/drivers/zdma/src/xzdma_sinit.c Normal file
View file

@ -0,0 +1,103 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xzdma_sinit.c
*
* This file contains static initialization methods for Xilinx ZDMA core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vns 2/27/15 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xzdma.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* XZDma_LookupConfig returns a reference to an XZDma_Config structure
* based on the unique device id, <i>DeviceId</i>. The return value will refer
* to an entry in the device configuration table defined in the xzdma_g.c
* file.
*
* @param DeviceId is the unique device ID of the device for the lookup
* operation.
*
* @return CfgPtr is a reference to a config record in the configuration
* table (in xzdma_g.c) corresponding to <i>DeviceId</i>, or
* NULL if no match is found.
*
* @note None.
******************************************************************************/
XZDma_Config *XZDma_LookupConfig(u16 DeviceId)
{
extern XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES];
XZDma_Config *CfgPtr = NULL;
u32 Index;
/* Checks all the instances */
for (Index = (u32)0x0; Index < (u32)(XPAR_XZDMA_NUM_INSTANCES);
Index++) {
if (XZDma_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XZDma_ConfigTable[Index];
break;
}
}
return (XZDma_Config *)CfgPtr;
}