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bsp: a53: added memory attribute definition in xil_mmu.h

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This patch adds various memory attribute definition
which can be used along with xil_settlbattributes API to
mark certain memory region with required attributes
such as cacheable or non-cacheable, inner/outer/non shareable
or executable or not etc.

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2015-07-27 18:56:16 +05:30 • committed by Nava kishore Manne
parent 39f94f2135
commit 1f3de84cd2
1 changed files with 26 additions and 0 deletions
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26
lib/bsp/standalone/src/cortexa53/64bit/xil_mmu.h
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@ -66,6 +66,32 @@ extern "C" {
/************************** Constant Definitions *****************************/
/* Memory type */
#define NORM_NONCACHE 0x401UL /* Normal Non-cacheable*/
#define STRONG_ORDERED 0x409UL /* Strongly ordered (Device-nGnRnE)*/
#define DEVICE_MEMORY 0x40DUL /* Device memory (Device-nGnRE)*/
#define RESERVED 0x0UL /* reserved memory*/
/* Normal write-through cacheable inner shareable*/
#define NORM_WT_CACHE 0x711UL
/* Normal write back cacheable inner-shareable */
#define NORM_WB_CACHE 0x705UL
/*
* shareability attribute only applicable to
* normal cacheable memory
*/
#define INNER_SHAREABLE (0x3 << 8)UL
#define OUTER_SHAREABLE (0x2 << 8)UL
#define NON_SHAREABLE (~(0x3 << 8))UL
/* Execution type */
#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54))UL
/* Security type */
#define NON_SECURE (0x1 << 5)UL
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/