dptx: Changed stream indices to start from 0 instead of 1.
Next IP documentation release will follow this convention as well. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
parent
d2697a6631
commit
91575b5dc2
6 changed files with 174 additions and 166 deletions
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@ -269,24 +269,24 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr)
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u8 Edid[XDPTX_EDID_SIZE];
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/* Set the bits per color. If not set, the default is 6. */
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID1, 8);
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID0, 8);
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/* Set synchronous clock mode. */
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XDptx_CfgMsaEnSynchClkMode(InstancePtr, XDPTX_STREAM_ID1, 1);
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XDptx_CfgMsaEnSynchClkMode(InstancePtr, XDPTX_STREAM_ID0, 1);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID0);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID4);
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/* Choose a method for selecting the video mode. There are 3 ways to do this:
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* 1) Use the preferred timing from the monitor's EDID:
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* u8 Edid[XDPTX_EDID_SIZE];
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* XDptx_GetEdid(InstancePtr, Edid);
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* XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr, XDPTX_STREAM_ID1, Edid);
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* XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr, XDPTX_STREAM_ID0, Edid);
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*
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* 2) Use a standard video timing mode (see mode_table.h):
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* XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID1,
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* XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID0,
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XDPTX_VM_640x480_60_P);
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*
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* 3) Use a custom configuration for the main stream attributes (MSA):
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@ -302,16 +302,16 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr)
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* MsaConfigCustom.Dmt.VFrontPorch = 1;
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* MsaConfigCustom.Dmt.VSyncPulseWidth = 3;
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* MsaConfigCustom.Dmt.VBackPorch = 38;
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* XDptx_CfgMsaUseCustom(InstancePtr, XDPTX_STREAM_ID1,
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* XDptx_CfgMsaUseCustom(InstancePtr, XDPTX_STREAM_ID0,
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* &MsaConfigCustom, 1);
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*/
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Status = XDptx_GetEdid(InstancePtr, Edid);
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if (Status == XST_SUCCESS) {
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XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr,
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XDPTX_STREAM_ID1, Edid);
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XDPTX_STREAM_ID0, Edid);
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}
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else {
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XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID1,
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XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID0,
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XDPTX_VM_640x480_60_P);
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}
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@ -327,7 +327,7 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr)
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XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0);
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/* Set the DisplayPort TX video mode. */
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XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID1);
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XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID0);
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/* Configure video stream source or generator here. These function need
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* to be implemented in order for video to be displayed and is hardware
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@ -79,10 +79,10 @@
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/* Define the mapping between sinks and streams. The sink numbers are in the
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* order that they are discovered by the XDptx_FindAccessibleDpDevices driver
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* function. */
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#define STREAM1_USE_SINKNUM 0
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#define STREAM2_USE_SINKNUM 1
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#define STREAM3_USE_SINKNUM 2
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#define STREAM4_USE_SINKNUM 3
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#define STREAM0_USE_SINKNUM 0
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#define STREAM1_USE_SINKNUM 1
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#define STREAM2_USE_SINKNUM 2
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#define STREAM3_USE_SINKNUM 3
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#endif
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/* The video resolution from the display mode timings (DMT) table to use for
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@ -92,6 +92,9 @@
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/* The color depth (bits per color component) to use for each stream. */
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#define USE_BPC 8
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/* Some MST configurations require delays when sending sideband messages. */
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#define USE_DELAYS_FOR_MST
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/**************************** Function Prototypes *****************************/
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u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId);
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@ -221,14 +224,15 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr)
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return XST_FAILURE;
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}
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/* If required, add delays in MST mode. */
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#ifdef USE_DELAYS_FOR_MST
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InstancePtr->AuxDelayUs = 30000;
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InstancePtr->SbMsgDelayUs = 100000;
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#endif
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID0);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID4);
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#ifdef ALLOCATE_FROM_SINKLIST
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xil_printf("Find topology >>>\n");
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@ -247,11 +251,11 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr)
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/* Enable multi-stream transport (MST) mode for this example. */
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XDptx_MstCfgModeEnable(InstancePtr);
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for (StreamIndex = 0; StreamIndex < NumStreams; StreamIndex++) {
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XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID1 +
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XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID0 +
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StreamIndex);
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}
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for (StreamIndex = NumStreams; StreamIndex < 4; StreamIndex++) {
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XDptx_MstCfgStreamDisable(InstancePtr, XDPTX_STREAM_ID1 +
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XDptx_MstCfgStreamDisable(InstancePtr, XDPTX_STREAM_ID0 +
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StreamIndex);
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}
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@ -259,24 +263,28 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr)
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u8 Lct;
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u8 Rad[15];
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) {
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0)) {
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Lct = 2; Rad[0] = 8;
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XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID0, Lct, Rad);
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}
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) {
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Lct = 3; Rad[0] = 1; Rad[1] = 8;
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XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID1, Lct, Rad);
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}
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) {
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Lct = 3; Rad[0] = 1; Rad[1] = 8;
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Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 8;
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XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID2, Lct, Rad);
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}
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) {
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Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 8;
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XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID3, Lct, Rad);
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}
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID4)) {
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Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 9;
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XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID4, Lct, Rad);
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XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID3, Lct, Rad);
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}
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#else
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0)) {
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XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID0,
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STREAM0_USE_SINKNUM);
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}
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) {
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XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID1,
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STREAM1_USE_SINKNUM);
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@ -289,25 +297,21 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr)
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XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID3,
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STREAM3_USE_SINKNUM);
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}
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID4)) {
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XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID4,
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STREAM4_USE_SINKNUM);
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}
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#endif
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/* Disable MST for now. */
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XDptx_MstDisable(InstancePtr);
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for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1 +
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0 +
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StreamIndex)) {
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID1 +
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID0 +
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StreamIndex, Bpc);
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XDptx_CfgMsaEnSynchClkMode(InstancePtr,
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XDPTX_STREAM_ID1 + StreamIndex, 1);
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XDPTX_STREAM_ID0 + StreamIndex, 1);
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XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
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XDPTX_STREAM_ID1 + StreamIndex, VideoMode);
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XDPTX_STREAM_ID0 + StreamIndex, VideoMode);
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}
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}
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@ -321,9 +325,9 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr)
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/* Set the video modes for each stream. */
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for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1 +
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0 +
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StreamIndex)) {
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XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID1 +
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XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID0 +
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StreamIndex);
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}
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}
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@ -144,11 +144,11 @@
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in microseconds. */
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/* @} */
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/** @name DPTX core registers: Main stream attributes for SST / MST STREAM1.
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/** @name DPTX core registers: Main stream attributes for SST / MST STREAM0.
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* @{
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*/
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#define XDPTX_STREAM1_MSA_START 0x0180 /**< Start of the MSA registers
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for stream 1. */
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#define XDPTX_STREAM0_MSA_START 0x0180 /**< Start of the MSA registers
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for stream 0. */
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#define XDPTX_MAIN_STREAM_HTOTAL 0x0180 /**< Total number of clocks in
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the horizontal framing
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period. */
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@ -297,33 +297,33 @@
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extension packet. */
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/* @} */
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/** @name DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4.
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/** @name DPTX core registers: Main stream attributes for MST STREAM1, 2, and 3.
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* @{
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*/
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#define XDPTX_STREAM2_MSA_START 0x0500 /**< Start of the MSA registers
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#define XDPTX_STREAM1_MSA_START 0x0500 /**< Start of the MSA registers
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for stream 1. */
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#define XDPTX_STREAM1_MSA_START_OFFSET (XDPTX_STREAM1_MSA_START - \
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XDPTX_STREAM0_MSA_START) /**< The MSA registers for
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stream 1 are at an
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offset from the
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corresponding registers
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of stream 0. */
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#define XDPTX_STREAM2_MSA_START 0x0550 /**< Start of the MSA registers
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for stream 2. */
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#define XDPTX_STREAM2_MSA_START_OFFSET (XDPTX_STREAM2_MSA_START - \
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XDPTX_STREAM1_MSA_START) /**< The MSA registers for
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XDPTX_STREAM0_MSA_START) /**< The MSA registers for
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stream 2 are at an
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offset from the
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corresponding registers
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of stream 1. */
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#define XDPTX_STREAM3_MSA_START 0x0550 /**< Start of the MSA registers
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of stream 0. */
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#define XDPTX_STREAM3_MSA_START 0x05A0 /**< Start of the MSA registers
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for stream 3. */
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#define XDPTX_STREAM3_MSA_START_OFFSET (XDPTX_STREAM3_MSA_START - \
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XDPTX_STREAM1_MSA_START) /**< The MSA registers for
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XDPTX_STREAM0_MSA_START) /**< The MSA registers for
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stream 3 are at an
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offset from the
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corresponding registers
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of stream 1. */
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#define XDPTX_STREAM4_MSA_START 0x05A0 /**< Start of the MSA registers
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for stream 4. */
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#define XDPTX_STREAM4_MSA_START_OFFSET (XDPTX_STREAM4_MSA_START - \
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XDPTX_STREAM1_MSA_START) /**< The MSA registers for
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stream 4 are at an
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offset from the
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corresponding registers
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of stream 1. */
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of stream 0. */
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/* @} */
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#define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 /**< Virtual channel payload
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@ -365,13 +365,13 @@
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0x3 /**< Pseudo random bit sequence
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7 transmitted. */
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/* 0x01C: SOFTWARE_RESET */
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#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK \
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#define XDPTX_SOFT_RESET_VIDEO_STREAM0_MASK \
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0x00000001 /**< Reset video logic. */
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#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK \
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#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK \
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0x00000002 /**< Reset video logic. */
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#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK \
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#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK \
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0x00000004 /**< Reset video logic. */
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#define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK \
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#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK \
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0x00000008 /**< Reset video logic. */
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#define XDPTX_SOFT_RESET_AUX_MASK \
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0x00000080 /**< Reset AUX logic. */
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@ -1165,10 +1165,10 @@
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/** @name Stream identification.
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* @{
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*/
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#define XDPTX_STREAM_ID0 0
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#define XDPTX_STREAM_ID1 1
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#define XDPTX_STREAM_ID2 2
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#define XDPTX_STREAM_ID3 3
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#define XDPTX_STREAM_ID4 4
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/* @} */
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/** @name Sideband message codes when the driver is in MST mode.
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@ -254,6 +254,10 @@ u32 XDptx_MstCapable(XDptx *InstancePtr)
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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if (InstancePtr->Config.MstSupport == 0) {
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return XST_NO_FEATURE;
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}
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/* Check that the RX device has a DisplayPort Configuration Data (DPCD)
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* version greater than or equal to 1.2 to be able to support MST
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* functionality. */
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@ -402,11 +406,11 @@ u8 XDptx_MstStreamIsEnabled(XDptx *InstancePtr, u8 Stream)
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{
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid((Stream == XDPTX_STREAM_ID1) ||
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(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
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(Stream == XDPTX_STREAM_ID4));
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Xil_AssertNonvoid((Stream == XDPTX_STREAM_ID0) ||
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(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
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(Stream == XDPTX_STREAM_ID3));
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return InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable;
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return InstancePtr->MstStreamConfig[Stream].MstStreamEnable;
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}
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/******************************************************************************/
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@ -426,11 +430,11 @@ void XDptx_MstCfgStreamEnable(XDptx *InstancePtr, u8 Stream)
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{
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
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(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
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(Stream == XDPTX_STREAM_ID4));
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Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
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(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
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(Stream == XDPTX_STREAM_ID3));
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InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable = 1;
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InstancePtr->MstStreamConfig[Stream].MstStreamEnable = 1;
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}
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/******************************************************************************/
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@ -450,11 +454,11 @@ void XDptx_MstCfgStreamDisable(XDptx *InstancePtr, u8 Stream)
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{
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
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(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
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(Stream == XDPTX_STREAM_ID4));
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Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
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(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
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(Stream == XDPTX_STREAM_ID3));
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InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable = 0;
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InstancePtr->MstStreamConfig[Stream].MstStreamEnable = 0;
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}
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/******************************************************************************/
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@ -485,11 +489,11 @@ void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
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(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
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(Stream == XDPTX_STREAM_ID4));
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Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
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(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
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(Stream == XDPTX_STREAM_ID3));
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|
||||
MstStream = &InstancePtr->MstStreamConfig[Stream - 1];
|
||||
MstStream = &InstancePtr->MstStreamConfig[Stream];
|
||||
Topology = &InstancePtr->Topology;
|
||||
|
||||
MstStream->LinkCountTotal = Topology->SinkList[SinkNum]->LinkCountTotal;
|
||||
|
@ -526,13 +530,13 @@ void XDptx_SetStreamSinkRad(XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal,
|
|||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
Xil_AssertVoid(LinkCountTotal > 0);
|
||||
Xil_AssertVoid(RelativeAddress != NULL);
|
||||
|
||||
MstStream = &InstancePtr->MstStreamConfig[Stream - 1];
|
||||
MstStream = &InstancePtr->MstStreamConfig[Stream];
|
||||
|
||||
MstStream->LinkCountTotal = LinkCountTotal;
|
||||
for (Index = 0; Index < MstStream->LinkCountTotal - 1; Index++) {
|
||||
|
@ -688,7 +692,7 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr)
|
|||
MstStream = &InstancePtr->MstStreamConfig[StreamIndex];
|
||||
MsaConfig = &InstancePtr->MsaConfig[StreamIndex];
|
||||
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex + 1)) {
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex)) {
|
||||
Status = XDptx_AllocatePayloadVcIdTable(InstancePtr,
|
||||
MstStream->LinkCountTotal,
|
||||
MstStream->RelativeAddress, StreamIndex + 1,
|
||||
|
@ -709,7 +713,7 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr)
|
|||
for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
|
||||
MstStream = &InstancePtr->MstStreamConfig[StreamIndex];
|
||||
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex + 1)) {
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex)) {
|
||||
Status = XDptx_SendSbMsgAllocatePayload(InstancePtr,
|
||||
MstStream->LinkCountTotal,
|
||||
MstStream->RelativeAddress, StreamIndex + 1,
|
||||
|
|
|
@ -188,13 +188,13 @@ u32 XDptx_SelfTest(XDptx *InstancePtr)
|
|||
StreamOffset = 0;
|
||||
}
|
||||
else if (StreamIndex == 1) {
|
||||
StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET;
|
||||
StreamOffset = XDPTX_STREAM1_MSA_START_OFFSET;
|
||||
}
|
||||
else if (StreamIndex == 2) {
|
||||
StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET;
|
||||
StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET;
|
||||
}
|
||||
else if (StreamIndex == 3) {
|
||||
StreamOffset = XDPTX_STREAM4_MSA_START_OFFSET;
|
||||
StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET;
|
||||
}
|
||||
|
||||
for (Index = 0; Index < 20; Index++) {
|
||||
|
|
|
@ -111,11 +111,11 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream)
|
|||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream - 1];
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
LinkConfig = &InstancePtr->LinkConfig;
|
||||
|
||||
/* Verify the rest of the values used. */
|
||||
|
@ -280,11 +280,11 @@ void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream,
|
|||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream - 1];
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
|
||||
/* Configure the MSA values from the display monitor DMT table. */
|
||||
MsaConfig->Dmt.HResolution = XDptx_DmtModes[VideoMode].HResolution;
|
||||
|
@ -331,12 +331,12 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream, u8 *Edid)
|
|||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
Xil_AssertVoid(Edid != NULL);
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream - 1];
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
Ptm = &Edid[XDPTX_EDID_PTM];
|
||||
|
||||
/* Configure the MSA values with the PTM information as
|
||||
|
@ -440,12 +440,12 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream,
|
|||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
Xil_AssertVoid(MsaConfigCustom != NULL);
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream - 1];
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
|
||||
/* Copy the MSA values from the user configuration structure. */
|
||||
MsaConfig->Dmt.HResolution = MsaConfigCustom->Dmt.HResolution;
|
||||
|
@ -500,14 +500,14 @@ void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor)
|
|||
{
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
|
||||
(BitsPerColor == 10) || (BitsPerColor == 12) ||
|
||||
(BitsPerColor == 16));
|
||||
|
||||
InstancePtr->MsaConfig[Stream - 1].BitsPerColor = BitsPerColor;
|
||||
InstancePtr->MsaConfig[Stream].BitsPerColor = BitsPerColor;
|
||||
|
||||
/* Calculate the rest of the MSA values. */
|
||||
XDptx_CfgMsaRecalculate(InstancePtr, Stream);
|
||||
|
@ -534,12 +534,12 @@ void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable)
|
|||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
Xil_AssertVoid((Enable == 0) || (Enable == 1));
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream - 1];
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
|
||||
MsaConfig->SynchronousClockMode = Enable;
|
||||
|
||||
|
@ -572,9 +572,9 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream)
|
|||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
XDptx_ClearMsaValues(InstancePtr, Stream);
|
||||
XDptx_SetMsaValues(InstancePtr, Stream);
|
||||
|
@ -596,58 +596,58 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream)
|
|||
void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream)
|
||||
{
|
||||
XDptx_Config *Config;
|
||||
u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET,
|
||||
XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET};
|
||||
u32 StreamOffset[4] = {0, XDPTX_STREAM1_MSA_START_OFFSET,
|
||||
XDPTX_STREAM2_MSA_START_OFFSET, XDPTX_STREAM3_MSA_START_OFFSET};
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
Config = &InstancePtr->Config;
|
||||
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_STREAM0 + (Stream - 1) * 4, 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_STREAM0 + (Stream) * 4, 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT +
|
||||
StreamOffset[Stream - 1], 0);
|
||||
StreamOffset[Stream], 0);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
|
@ -668,70 +668,70 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream)
|
|||
{
|
||||
XDptx_Config *Config;
|
||||
XDptx_MainStreamAttributes *MsaConfig;
|
||||
u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET,
|
||||
XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET};
|
||||
u32 StreamOffset[4] = {0, XDPTX_STREAM1_MSA_START_OFFSET,
|
||||
XDPTX_STREAM2_MSA_START_OFFSET, XDPTX_STREAM3_MSA_START_OFFSET};
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) ||
|
||||
(Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) ||
|
||||
(Stream == XDPTX_STREAM_ID4));
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
Config = &InstancePtr->Config;
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream - 1];
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
|
||||
/* Set the main stream attributes to the associated DisplayPort TX core
|
||||
* registers. */
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL +
|
||||
StreamOffset[Stream - 1], MsaConfig->HClkTotal);
|
||||
StreamOffset[Stream], MsaConfig->HClkTotal);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL +
|
||||
StreamOffset[Stream - 1], MsaConfig->VClkTotal);
|
||||
StreamOffset[Stream], MsaConfig->VClkTotal);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY +
|
||||
StreamOffset[Stream - 1], MsaConfig->Dmt.HSyncPolarity |
|
||||
StreamOffset[Stream], MsaConfig->Dmt.HSyncPolarity |
|
||||
(MsaConfig->Dmt.VSyncPolarity <<
|
||||
XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH +
|
||||
StreamOffset[Stream - 1], MsaConfig->Dmt.HSyncPulseWidth);
|
||||
StreamOffset[Stream], MsaConfig->Dmt.HSyncPulseWidth);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH +
|
||||
StreamOffset[Stream - 1], MsaConfig->Dmt.VSyncPulseWidth);
|
||||
StreamOffset[Stream], MsaConfig->Dmt.VSyncPulseWidth);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES +
|
||||
StreamOffset[Stream - 1], MsaConfig->Dmt.HResolution);
|
||||
StreamOffset[Stream], MsaConfig->Dmt.HResolution);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES +
|
||||
StreamOffset[Stream - 1], MsaConfig->Dmt.VResolution);
|
||||
StreamOffset[Stream], MsaConfig->Dmt.VResolution);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART +
|
||||
StreamOffset[Stream - 1], MsaConfig->HStart);
|
||||
StreamOffset[Stream], MsaConfig->HStart);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART +
|
||||
StreamOffset[Stream - 1], MsaConfig->VStart);
|
||||
StreamOffset[Stream], MsaConfig->VStart);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 +
|
||||
StreamOffset[Stream - 1], MsaConfig->Misc0);
|
||||
StreamOffset[Stream], MsaConfig->Misc0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 +
|
||||
StreamOffset[Stream - 1], MsaConfig->Misc1);
|
||||
StreamOffset[Stream], MsaConfig->Misc1);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID +
|
||||
StreamOffset[Stream - 1], MsaConfig->Dmt.PixelClkKhz);
|
||||
StreamOffset[Stream], MsaConfig->Dmt.PixelClkKhz);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID +
|
||||
StreamOffset[Stream - 1], MsaConfig->NVid);
|
||||
StreamOffset[Stream], MsaConfig->NVid);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH +
|
||||
StreamOffset[Stream - 1], MsaConfig->UserPixelWidth);
|
||||
StreamOffset[Stream], MsaConfig->UserPixelWidth);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE +
|
||||
StreamOffset[Stream - 1], MsaConfig->DataPerLane);
|
||||
StreamOffset[Stream], MsaConfig->DataPerLane);
|
||||
|
||||
/* Set the transfer unit values to the associated DisplayPort TX core
|
||||
* registers. */
|
||||
if (InstancePtr->MstEnable == 1) {
|
||||
XDptx_WriteReg(Config->BaseAddr,
|
||||
XDPTX_STREAM0 + (Stream - 1) * 4,
|
||||
XDPTX_STREAM0 + (Stream) * 4,
|
||||
((MsaConfig->AvgBytesPerTU / 1000) << 16) |
|
||||
(MsaConfig->AvgBytesPerTU % 1000));
|
||||
}
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE +
|
||||
StreamOffset[Stream - 1], MsaConfig->TransferUnitSize);
|
||||
StreamOffset[Stream], MsaConfig->TransferUnitSize);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU +
|
||||
StreamOffset[Stream - 1], MsaConfig->AvgBytesPerTU / 1000);
|
||||
StreamOffset[Stream], MsaConfig->AvgBytesPerTU / 1000);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU +
|
||||
StreamOffset[Stream - 1], MsaConfig->AvgBytesPerTU % 1000);
|
||||
StreamOffset[Stream], MsaConfig->AvgBytesPerTU % 1000);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT +
|
||||
StreamOffset[Stream - 1], MsaConfig->InitWait);
|
||||
StreamOffset[Stream], MsaConfig->InitWait);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
|
@ -755,7 +755,7 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream)
|
|||
static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel)
|
||||
{
|
||||
XDptx_MainStreamAttributes *MsaConfig =
|
||||
&InstancePtr->MsaConfig[Stream - 1];
|
||||
&InstancePtr->MsaConfig[Stream];
|
||||
XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
|
||||
double PeakPixelBw;
|
||||
u32 LinkBw;
|
||||
|
@ -770,18 +770,18 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel)
|
|||
LinkBw = (LinkConfig->LaneCount * LinkConfig->LinkRate * 27);
|
||||
|
||||
/* Calculate the payload bandiwdth number (PBN). */
|
||||
InstancePtr->MstStreamConfig[Stream - 1].MstPbn =
|
||||
InstancePtr->MstStreamConfig[Stream].MstPbn =
|
||||
1.006 * PeakPixelBw * ((double)64 / 54);
|
||||
/* Ceil - round up if required, avoiding overhead of math.h. */
|
||||
if ((double)(1.006 * PeakPixelBw * ((double)64 / 54)) >
|
||||
((double)InstancePtr->MstStreamConfig[Stream - 1].MstPbn)) {
|
||||
InstancePtr->MstStreamConfig[Stream - 1].MstPbn++;
|
||||
((double)InstancePtr->MstStreamConfig[Stream].MstPbn)) {
|
||||
InstancePtr->MstStreamConfig[Stream].MstPbn++;
|
||||
}
|
||||
|
||||
/* Calculate the average stream symbol time slots per MTP. */
|
||||
Average_StreamSymbolTimeSlotsPerMTP = (64.0 * PeakPixelBw / LinkBw);
|
||||
MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP = (54.0 *
|
||||
((double)InstancePtr->MstStreamConfig[Stream - 1].MstPbn /
|
||||
((double)InstancePtr->MstStreamConfig[Stream].MstPbn /
|
||||
LinkBw));
|
||||
|
||||
/* The target value to be found needs to follow the condition:
|
||||
|
@ -826,7 +826,7 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel)
|
|||
}
|
||||
|
||||
/* Determine the PBN for the stream. */
|
||||
InstancePtr->MstStreamConfig[Stream - 1].MstPbn =
|
||||
InstancePtr->MstStreamConfig[Stream].MstPbn =
|
||||
MsaConfig->TransferUnitSize *
|
||||
(LinkConfig->LaneCount * LinkConfig->LinkRate / 2);
|
||||
}
|
||||
|
|
Loading…
Add table
Reference in a new issue