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sw_apps:zynqmp_fsbl: Added power on reset bit fields

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While releasing resets, power on reset bit fields of
the corresponding CPU core also considered now.
These bit fields are added in RST_FPD_APU register from RTL 5.0.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This commit is contained in:
Sarat Chand Savitala 2015-03-01 16:52:09 +05:30 • committed by Nava kishore Manne
parent 4837f2baf5
commit 918e66a41a
2 changed files with 19 additions and 8 deletions
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22
lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c
View file

@ -171,8 +171,9 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
* Release reset
*/
RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU0_RESET_MASK);
RegValue &= ~(CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU0_RESET_MASK |
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK);
XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
/**
@ -199,8 +200,9 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
* Release reset
*/
RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU1_RESET_MASK);
RegValue &= ~(CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU1_RESET_MASK |
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK);
XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
/**
@ -227,8 +229,10 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
* Release reset
*/
RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK);
RegValue &= ~(CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK |
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_MASK);
XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
/**
@ -255,8 +259,10 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
* Release reset
*/
RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK);
RegValue &= ~(CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK |
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_MASK);
XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
/**

5
lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h
View file

@ -175,6 +175,11 @@ extern "C" {
#define CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK 0X00000004U
#define CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK 0X00000008U
#define CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_MASK 0X00002000U
#define CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_MASK 0X00001000U
#define CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK 0X00000800U
#define CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK 0X00000400U
/* crl_apb */
/**