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Xilinx Embedded Software (embeddedsw) Development
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Sarat Chand Savitala 918e66a41a sw_apps:zynqmp_fsbl: Added power on reset bit fields 
While releasing resets, power on reset bit fields of
the corresponding CPU core also considered now.
These bit fields are added in RST_FPD_APU register from RTL 5.0.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-03-11 14:33:53 +05:30
doc Change Log for 2015.1 2015-03-01 09:56:03 +05:30
lib sw_apps:zynqmp_fsbl: Added power on reset bit fields 2015-03-11 14:33:53 +05:30
XilinxProcessorIPLib/drivers vtc: Modified vtc_v7_0 source files. 2015-02-27 19:06:52 +05:30