Xilinx Embedded Software (embeddedsw) Development
![]() While releasing resets, power on reset bit fields of the corresponding CPU core also considered now. These bit fields are added in RST_FPD_APU register from RTL 5.0. Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com> |
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XilinxProcessorIPLib/drivers |