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gqspips: Clear and disable DMA interrupts initially

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Clear and disable DMA interrupts/status register initially.
Correct DMA_CTRL reset value.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
Harini Katakam 2015-03-19 12:29:15 +05:30 • committed by Nava kishore Manne
parent 2b3a7c5e4c
commit b337ae9801
3 changed files with 24 additions and 4 deletions
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21
XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.c
View file

@ -45,6 +45,7 @@
* 1.0 hk 08/21/14 First release
* sk 03/13/15 Added IO mode support.
* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
* Clear and disbale DMA interrupts/status in abort.
*
* </pre>
*
@ -245,14 +246,28 @@ void XQspiPsu_Reset(XQspiPsu *InstancePtr)
void XQspiPsu_Abort(XQspiPsu *InstancePtr)
{
u32 ConfigReg;
u32 IntrStatus, ConfigReg;
IntrStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_ISR_OFFSET);
/* Clear and disable interrupts */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_ISR_OFFSET,
XQSPIPSU_ISR_OFFSET, IntrStatus | XQSPIPSU_ISR_WR_TO_CLR_MASK);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_ISR_OFFSET) | XQSPIPSU_ISR_WR_TO_CLR_MASK);
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET));
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_STS_OFFSET,
XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_STS_OFFSET) |
XQSPIPSU_QSPIDMA_DST_STS_WTC);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_IDR_OFFSET, XQSPIPSU_IDR_ALL_MASK);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK);
/* Clear FIFO */
if((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,

1
XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.h
View file

@ -87,6 +87,7 @@
* 1.0 hk 08/21/14 First release
* sk 03/13/15 Added IO mode support.
* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
* Clear and disbale DMA interrupts/status in abort.
*
* </pre>
*

6
XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.h
View file

@ -43,6 +43,7 @@
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------.
* 1.0 hk 08/21/14 First release
* hk 03/18/15 Add DMA status register masks required.
*
* </pre>
*
@ -540,6 +541,8 @@ extern "C" {
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001
#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000
/**
* Register: XQSPIPSU_QSPIDMA_DST_CTRL
*/
@ -577,7 +580,7 @@ extern "C" {
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001
#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00
#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_STS
@ -613,6 +616,7 @@ extern "C" {
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FC
#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FE
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_EN