gqspips: Clear and disable DMA interrupts initially
Clear and disable DMA interrupts/status register initially. Correct DMA_CTRL reset value. Signed-off-by: Harini Katakam <harinik@xilinx.com>
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2b3a7c5e4c
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b337ae9801
3 changed files with 24 additions and 4 deletions
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@ -45,6 +45,7 @@
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* 1.0 hk 08/21/14 First release
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* sk 03/13/15 Added IO mode support.
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* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
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* Clear and disbale DMA interrupts/status in abort.
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*
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* </pre>
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*
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@ -245,14 +246,28 @@ void XQspiPsu_Reset(XQspiPsu *InstancePtr)
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void XQspiPsu_Abort(XQspiPsu *InstancePtr)
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{
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u32 ConfigReg;
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u32 IntrStatus, ConfigReg;
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IntrStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_ISR_OFFSET);
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/* Clear and disable interrupts */
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_ISR_OFFSET,
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XQSPIPSU_ISR_OFFSET, IntrStatus | XQSPIPSU_ISR_WR_TO_CLR_MASK);
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
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XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_ISR_OFFSET) | XQSPIPSU_ISR_WR_TO_CLR_MASK);
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XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET));
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_QSPIDMA_DST_STS_OFFSET,
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XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_QSPIDMA_DST_STS_OFFSET) |
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XQSPIPSU_QSPIDMA_DST_STS_WTC);
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_IDR_OFFSET, XQSPIPSU_IDR_ALL_MASK);
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
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XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK);
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/* Clear FIFO */
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if((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
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@ -87,6 +87,7 @@
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* 1.0 hk 08/21/14 First release
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* sk 03/13/15 Added IO mode support.
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* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
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* Clear and disbale DMA interrupts/status in abort.
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*
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* </pre>
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*
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@ -43,6 +43,7 @@
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* Ver Who Date Changes
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* ----- --- -------- -----------------------------------------------.
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* 1.0 hk 08/21/14 First release
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* hk 03/18/15 Add DMA status register masks required.
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*
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* </pre>
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*
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@ -540,6 +541,8 @@ extern "C" {
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#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1
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#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001
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#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000
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/**
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* Register: XQSPIPSU_QSPIDMA_DST_CTRL
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*/
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@ -577,7 +580,7 @@ extern "C" {
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#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1
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#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001
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#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00
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#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
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/**
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* Register: XQSPIPSU_QSPIDMA_DST_I_STS
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@ -613,6 +616,7 @@ extern "C" {
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#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002
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#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FC
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#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FE
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/**
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* Register: XQSPIPSU_QSPIDMA_DST_I_EN
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