v_csc: Driver for CSC core

HLS generated Layer 1 driver for csc core along with manually written layer 2. Pending update of driver tcl Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-05-27 08:11:26 +08:00 · 2015-05-27 08:11:26 +08:00 · c9796ae1ff
commit c9796ae1ff
parent 4baf4b5e6e
10 changed files with 3131 additions and 0 deletions
--- a/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.mdd
+++ b/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.mdd
@ -0,0 +1,18 @@
+# ==============================================================
+# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+# Version: 2015.1
+# Copyright (C) 2015 Xilinx Inc. All rights reserved.
+#
+# ==============================================================
+
+OPTION psf_version = 2.1;
+
+BEGIN driver v_csc
+
+ OPTION supported_peripherals = (v_csc_v1_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = v_csc;
+ OPTION version = 1.0;
+
+END driver
--- a/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.tcl
+++ b/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.tcl
@ -0,0 +1,23 @@
+# ==============================================================
+# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+# Version: 2015.1
+# Copyright (C) 2015 Xilinx Inc. All rights reserved.
+#
+# ==============================================================
+
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XV_csc" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_CTRL_BASEADDR" \
+        "C_S_AXI_CTRL_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xv_csc_g.c" "XV_csc" \
+        "DEVICE_ID" \
+        "C_S_AXI_CTRL_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_csc" \
+        "DEVICE_ID" \
+        "C_S_AXI_CTRL_BASEADDR" \
+        "C_S_AXI_CTRL_HIGHADDR"
+}
--- a/XilinxProcessorIPLib/drivers/v_csc/src/Makefile
+++ b/XilinxProcessorIPLib/drivers/v_csc/src/Makefile
@ -0,0 +1,34 @@
+# ==============================================================
+# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+# Version: 2015.1
+# Copyright (C) 2015 Xilinx Inc. All rights reserved.
+#
+# ==============================================================
+
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+
+libs:
+	echo "Compiling v_csc"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
--- a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.c
+++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.c
@ -0,0 +1,744 @@
+// ==============================================================
+// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+// Version: 2015.1
+// Copyright (C) 2015 Xilinx Inc. All rights reserved.
+//
+// ==============================================================
+
+/***************************** Include Files *********************************/
+#include "xv_csc.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XV_csc_CfgInitialize(XV_csc *InstancePtr, XV_csc_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Ctrl_BaseAddress = ConfigPtr->Ctrl_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XV_csc_Start(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL) & 0x80;
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XV_csc_IsDone(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XV_csc_IsIdle(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XV_csc_IsReady(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XV_csc_EnableAutoRestart(XV_csc *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, 0x80);
+}
+
+void XV_csc_DisableAutoRestart(XV_csc *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, 0);
+}
+
+void XV_csc_Set_HwReg_InVideoFormat(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_InVideoFormat(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_OutVideoFormat(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_OutVideoFormat(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_width(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_width(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_height(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_height(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_ColStart(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_ColStart(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_ColEnd(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_ColEnd(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_RowStart(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_RowStart(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_RowEnd(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_RowEnd(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K11(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K11(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K12(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K12(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K13(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K13(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K21(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K21(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K22(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K22(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K23(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K23(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K31(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K31(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K32(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K32(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K33(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K33(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_ROffset_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_ROffset_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_GOffset_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_GOffset_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_BOffset_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_BOffset_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_ClampMin_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_ClampMin_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_ClipMax_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_ClipMax_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K11_2(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K11_2(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K12_2(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K12_2(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K13_2(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K13_2(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K21_2(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K21_2(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K22_2(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K22_2(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K23_2(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K23_2(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K31_2(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K31_2(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K32_2(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K32_2(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_K33_2(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_K33_2(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_ROffset_2_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_ROffset_2_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_GOffset_2_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_GOffset_2_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_BOffset_2_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_BOffset_2_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_ClampMin_2_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_ClampMin_2_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA);
+    return Data;
+}
+
+void XV_csc_Set_HwReg_ClipMax_2_V(XV_csc *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA, Data);
+}
+
+u32 XV_csc_Get_HwReg_ClipMax_2_V(XV_csc *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA);
+    return Data;
+}
+
+void XV_csc_InterruptGlobalEnable(XV_csc *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_GIE, 1);
+}
+
+void XV_csc_InterruptGlobalDisable(XV_csc *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_GIE, 0);
+}
+
+void XV_csc_InterruptEnable(XV_csc *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER);
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER, Register | Mask);
+}
+
+void XV_csc_InterruptDisable(XV_csc *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER);
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER, Register & (~Mask));
+}
+
+void XV_csc_InterruptClear(XV_csc *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_ISR, Mask);
+}
+
+u32 XV_csc_InterruptGetEnabled(XV_csc *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER);
+}
+
+u32 XV_csc_InterruptGetStatus(XV_csc *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_ISR);
+}
--- a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.h
+++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.h
@ -0,0 +1,175 @@
+// ==============================================================
+// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+// Version: 2015.1
+// Copyright (C) 2015 Xilinx Inc. All rights reserved.
+//
+// ==============================================================
+
+#ifndef XV_CSC_H
+#define XV_CSC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xv_csc_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Ctrl_BaseAddress;
+} XV_csc_Config;
+#endif
+
+typedef struct {
+    u32 Ctrl_BaseAddress;
+    u32 IsReady;
+} XV_csc;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XV_csc_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XV_csc_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XV_csc_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XV_csc_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XV_csc_Initialize(XV_csc *InstancePtr, u16 DeviceId);
+XV_csc_Config* XV_csc_LookupConfig(u16 DeviceId);
+int XV_csc_CfgInitialize(XV_csc *InstancePtr, XV_csc_Config *ConfigPtr);
+#else
+int XV_csc_Initialize(XV_csc *InstancePtr, const char* InstanceName);
+int XV_csc_Release(XV_csc *InstancePtr);
+#endif
+
+void XV_csc_Start(XV_csc *InstancePtr);
+u32 XV_csc_IsDone(XV_csc *InstancePtr);
+u32 XV_csc_IsIdle(XV_csc *InstancePtr);
+u32 XV_csc_IsReady(XV_csc *InstancePtr);
+void XV_csc_EnableAutoRestart(XV_csc *InstancePtr);
+void XV_csc_DisableAutoRestart(XV_csc *InstancePtr);
+
+void XV_csc_Set_HwReg_InVideoFormat(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_InVideoFormat(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_OutVideoFormat(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_OutVideoFormat(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_width(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_width(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_height(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_height(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_ColStart(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_ColStart(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_ColEnd(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_ColEnd(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_RowStart(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_RowStart(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_RowEnd(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_RowEnd(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K11(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K11(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K12(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K12(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K13(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K13(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K21(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K21(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K22(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K22(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K23(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K23(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K31(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K31(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K32(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K32(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K33(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K33(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_ROffset_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_ROffset_V(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_GOffset_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_GOffset_V(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_BOffset_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_BOffset_V(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_ClampMin_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_ClampMin_V(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_ClipMax_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_ClipMax_V(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K11_2(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K11_2(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K12_2(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K12_2(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K13_2(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K13_2(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K21_2(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K21_2(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K22_2(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K22_2(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K23_2(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K23_2(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K31_2(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K31_2(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K32_2(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K32_2(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_K33_2(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_K33_2(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_ROffset_2_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_ROffset_2_V(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_GOffset_2_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_GOffset_2_V(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_BOffset_2_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_BOffset_2_V(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_ClampMin_2_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_ClampMin_2_V(XV_csc *InstancePtr);
+void XV_csc_Set_HwReg_ClipMax_2_V(XV_csc *InstancePtr, u32 Data);
+u32 XV_csc_Get_HwReg_ClipMax_2_V(XV_csc *InstancePtr);
+
+void XV_csc_InterruptGlobalEnable(XV_csc *InstancePtr);
+void XV_csc_InterruptGlobalDisable(XV_csc *InstancePtr);
+void XV_csc_InterruptEnable(XV_csc *InstancePtr, u32 Mask);
+void XV_csc_InterruptDisable(XV_csc *InstancePtr, u32 Mask);
+void XV_csc_InterruptClear(XV_csc *InstancePtr, u32 Mask);
+u32 XV_csc_InterruptGetEnabled(XV_csc *InstancePtr);
+u32 XV_csc_InterruptGetStatus(XV_csc *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_hw.h
+++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_hw.h
@ -0,0 +1,248 @@
+// ==============================================================
+// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+// Version: 2015.1
+// Copyright (C) 2015 Xilinx Inc. All rights reserved.
+//
+// ==============================================================
+
+// CTRL
+// 0x000 : Control signals
+//         bit 0  - ap_start (Read/Write/COH)
+//         bit 1  - ap_done (Read/COR)
+//         bit 2  - ap_idle (Read)
+//         bit 3  - ap_ready (Read)
+//         bit 7  - auto_restart (Read/Write)
+//         others - reserved
+// 0x004 : Global Interrupt Enable Register
+//         bit 0  - Global Interrupt Enable (Read/Write)
+//         others - reserved
+// 0x008 : IP Interrupt Enable Register (Read/Write)
+//         bit 0  - Channel 0 (ap_done)
+//         bit 1  - Channel 1 (ap_ready)
+//         others - reserved
+// 0x00c : IP Interrupt Status Register (Read/TOW)
+//         bit 0  - Channel 0 (ap_done)
+//         bit 1  - Channel 1 (ap_ready)
+//         others - reserved
+// 0x010 : Data signal of HwReg_InVideoFormat
+//         bit 7~0 - HwReg_InVideoFormat[7:0] (Read/Write)
+//         others  - reserved
+// 0x014 : reserved
+// 0x018 : Data signal of HwReg_OutVideoFormat
+//         bit 7~0 - HwReg_OutVideoFormat[7:0] (Read/Write)
+//         others  - reserved
+// 0x01c : reserved
+// 0x020 : Data signal of HwReg_width
+//         bit 15~0 - HwReg_width[15:0] (Read/Write)
+//         others   - reserved
+// 0x024 : reserved
+// 0x028 : Data signal of HwReg_height
+//         bit 15~0 - HwReg_height[15:0] (Read/Write)
+//         others   - reserved
+// 0x02c : reserved
+// 0x030 : Data signal of HwReg_ColStart
+//         bit 15~0 - HwReg_ColStart[15:0] (Read/Write)
+//         others   - reserved
+// 0x034 : reserved
+// 0x038 : Data signal of HwReg_ColEnd
+//         bit 15~0 - HwReg_ColEnd[15:0] (Read/Write)
+//         others   - reserved
+// 0x03c : reserved
+// 0x040 : Data signal of HwReg_RowStart
+//         bit 15~0 - HwReg_RowStart[15:0] (Read/Write)
+//         others   - reserved
+// 0x044 : reserved
+// 0x048 : Data signal of HwReg_RowEnd
+//         bit 15~0 - HwReg_RowEnd[15:0] (Read/Write)
+//         others   - reserved
+// 0x04c : reserved
+// 0x050 : Data signal of HwReg_K11
+//         bit 15~0 - HwReg_K11[15:0] (Read/Write)
+//         others   - reserved
+// 0x054 : reserved
+// 0x058 : Data signal of HwReg_K12
+//         bit 15~0 - HwReg_K12[15:0] (Read/Write)
+//         others   - reserved
+// 0x05c : reserved
+// 0x060 : Data signal of HwReg_K13
+//         bit 15~0 - HwReg_K13[15:0] (Read/Write)
+//         others   - reserved
+// 0x064 : reserved
+// 0x068 : Data signal of HwReg_K21
+//         bit 15~0 - HwReg_K21[15:0] (Read/Write)
+//         others   - reserved
+// 0x06c : reserved
+// 0x070 : Data signal of HwReg_K22
+//         bit 15~0 - HwReg_K22[15:0] (Read/Write)
+//         others   - reserved
+// 0x074 : reserved
+// 0x078 : Data signal of HwReg_K23
+//         bit 15~0 - HwReg_K23[15:0] (Read/Write)
+//         others   - reserved
+// 0x07c : reserved
+// 0x080 : Data signal of HwReg_K31
+//         bit 15~0 - HwReg_K31[15:0] (Read/Write)
+//         others   - reserved
+// 0x084 : reserved
+// 0x088 : Data signal of HwReg_K32
+//         bit 15~0 - HwReg_K32[15:0] (Read/Write)
+//         others   - reserved
+// 0x08c : reserved
+// 0x090 : Data signal of HwReg_K33
+//         bit 15~0 - HwReg_K33[15:0] (Read/Write)
+//         others   - reserved
+// 0x094 : reserved
+// 0x098 : Data signal of HwReg_ROffset_V
+//         bit 11~0 - HwReg_ROffset_V[11:0] (Read/Write)
+//         others   - reserved
+// 0x09c : reserved
+// 0x0a0 : Data signal of HwReg_GOffset_V
+//         bit 11~0 - HwReg_GOffset_V[11:0] (Read/Write)
+//         others   - reserved
+// 0x0a4 : reserved
+// 0x0a8 : Data signal of HwReg_BOffset_V
+//         bit 11~0 - HwReg_BOffset_V[11:0] (Read/Write)
+//         others   - reserved
+// 0x0ac : reserved
+// 0x0b0 : Data signal of HwReg_ClampMin_V
+//         bit 9~0 - HwReg_ClampMin_V[9:0] (Read/Write)
+//         others  - reserved
+// 0x0b4 : reserved
+// 0x0b8 : Data signal of HwReg_ClipMax_V
+//         bit 9~0 - HwReg_ClipMax_V[9:0] (Read/Write)
+//         others  - reserved
+// 0x0bc : reserved
+// 0x0c0 : Data signal of HwReg_K11_2
+//         bit 15~0 - HwReg_K11_2[15:0] (Read/Write)
+//         others   - reserved
+// 0x0c4 : reserved
+// 0x0c8 : Data signal of HwReg_K12_2
+//         bit 15~0 - HwReg_K12_2[15:0] (Read/Write)
+//         others   - reserved
+// 0x0cc : reserved
+// 0x0d0 : Data signal of HwReg_K13_2
+//         bit 15~0 - HwReg_K13_2[15:0] (Read/Write)
+//         others   - reserved
+// 0x0d4 : reserved
+// 0x0d8 : Data signal of HwReg_K21_2
+//         bit 15~0 - HwReg_K21_2[15:0] (Read/Write)
+//         others   - reserved
+// 0x0dc : reserved
+// 0x0e0 : Data signal of HwReg_K22_2
+//         bit 15~0 - HwReg_K22_2[15:0] (Read/Write)
+//         others   - reserved
+// 0x0e4 : reserved
+// 0x0e8 : Data signal of HwReg_K23_2
+//         bit 15~0 - HwReg_K23_2[15:0] (Read/Write)
+//         others   - reserved
+// 0x0ec : reserved
+// 0x0f0 : Data signal of HwReg_K31_2
+//         bit 15~0 - HwReg_K31_2[15:0] (Read/Write)
+//         others   - reserved
+// 0x0f4 : reserved
+// 0x0f8 : Data signal of HwReg_K32_2
+//         bit 15~0 - HwReg_K32_2[15:0] (Read/Write)
+//         others   - reserved
+// 0x0fc : reserved
+// 0x100 : Data signal of HwReg_K33_2
+//         bit 15~0 - HwReg_K33_2[15:0] (Read/Write)
+//         others   - reserved
+// 0x104 : reserved
+// 0x108 : Data signal of HwReg_ROffset_2_V
+//         bit 11~0 - HwReg_ROffset_2_V[11:0] (Read/Write)
+//         others   - reserved
+// 0x10c : reserved
+// 0x110 : Data signal of HwReg_GOffset_2_V
+//         bit 11~0 - HwReg_GOffset_2_V[11:0] (Read/Write)
+//         others   - reserved
+// 0x114 : reserved
+// 0x118 : Data signal of HwReg_BOffset_2_V
+//         bit 11~0 - HwReg_BOffset_2_V[11:0] (Read/Write)
+//         others   - reserved
+// 0x11c : reserved
+// 0x120 : Data signal of HwReg_ClampMin_2_V
+//         bit 9~0 - HwReg_ClampMin_2_V[9:0] (Read/Write)
+//         others  - reserved
+// 0x124 : reserved
+// 0x128 : Data signal of HwReg_ClipMax_2_V
+//         bit 9~0 - HwReg_ClipMax_2_V[9:0] (Read/Write)
+//         others  - reserved
+// 0x12c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XV_CSC_CTRL_ADDR_AP_CTRL                   0x000
+#define XV_CSC_CTRL_ADDR_GIE                       0x004
+#define XV_CSC_CTRL_ADDR_IER                       0x008
+#define XV_CSC_CTRL_ADDR_ISR                       0x00c
+#define XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA  0x010
+#define XV_CSC_CTRL_BITS_HWREG_INVIDEOFORMAT_DATA  8
+#define XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA 0x018
+#define XV_CSC_CTRL_BITS_HWREG_OUTVIDEOFORMAT_DATA 8
+#define XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA          0x020
+#define XV_CSC_CTRL_BITS_HWREG_WIDTH_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA         0x028
+#define XV_CSC_CTRL_BITS_HWREG_HEIGHT_DATA         16
+#define XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA       0x030
+#define XV_CSC_CTRL_BITS_HWREG_COLSTART_DATA       16
+#define XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA         0x038
+#define XV_CSC_CTRL_BITS_HWREG_COLEND_DATA         16
+#define XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA       0x040
+#define XV_CSC_CTRL_BITS_HWREG_ROWSTART_DATA       16
+#define XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA         0x048
+#define XV_CSC_CTRL_BITS_HWREG_ROWEND_DATA         16
+#define XV_CSC_CTRL_ADDR_HWREG_K11_DATA            0x050
+#define XV_CSC_CTRL_BITS_HWREG_K11_DATA            16
+#define XV_CSC_CTRL_ADDR_HWREG_K12_DATA            0x058
+#define XV_CSC_CTRL_BITS_HWREG_K12_DATA            16
+#define XV_CSC_CTRL_ADDR_HWREG_K13_DATA            0x060
+#define XV_CSC_CTRL_BITS_HWREG_K13_DATA            16
+#define XV_CSC_CTRL_ADDR_HWREG_K21_DATA            0x068
+#define XV_CSC_CTRL_BITS_HWREG_K21_DATA            16
+#define XV_CSC_CTRL_ADDR_HWREG_K22_DATA            0x070
+#define XV_CSC_CTRL_BITS_HWREG_K22_DATA            16
+#define XV_CSC_CTRL_ADDR_HWREG_K23_DATA            0x078
+#define XV_CSC_CTRL_BITS_HWREG_K23_DATA            16
+#define XV_CSC_CTRL_ADDR_HWREG_K31_DATA            0x080
+#define XV_CSC_CTRL_BITS_HWREG_K31_DATA            16
+#define XV_CSC_CTRL_ADDR_HWREG_K32_DATA            0x088
+#define XV_CSC_CTRL_BITS_HWREG_K32_DATA            16
+#define XV_CSC_CTRL_ADDR_HWREG_K33_DATA            0x090
+#define XV_CSC_CTRL_BITS_HWREG_K33_DATA            16
+#define XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA      0x098
+#define XV_CSC_CTRL_BITS_HWREG_ROFFSET_V_DATA      12
+#define XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA      0x0a0
+#define XV_CSC_CTRL_BITS_HWREG_GOFFSET_V_DATA      12
+#define XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA      0x0a8
+#define XV_CSC_CTRL_BITS_HWREG_BOFFSET_V_DATA      12
+#define XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA     0x0b0
+#define XV_CSC_CTRL_BITS_HWREG_CLAMPMIN_V_DATA     10
+#define XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA      0x0b8
+#define XV_CSC_CTRL_BITS_HWREG_CLIPMAX_V_DATA      10
+#define XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA          0x0c0
+#define XV_CSC_CTRL_BITS_HWREG_K11_2_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA          0x0c8
+#define XV_CSC_CTRL_BITS_HWREG_K12_2_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA          0x0d0
+#define XV_CSC_CTRL_BITS_HWREG_K13_2_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA          0x0d8
+#define XV_CSC_CTRL_BITS_HWREG_K21_2_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA          0x0e0
+#define XV_CSC_CTRL_BITS_HWREG_K22_2_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA          0x0e8
+#define XV_CSC_CTRL_BITS_HWREG_K23_2_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA          0x0f0
+#define XV_CSC_CTRL_BITS_HWREG_K31_2_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA          0x0f8
+#define XV_CSC_CTRL_BITS_HWREG_K32_2_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA          0x100
+#define XV_CSC_CTRL_BITS_HWREG_K33_2_DATA          16
+#define XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA    0x108
+#define XV_CSC_CTRL_BITS_HWREG_ROFFSET_2_V_DATA    12
+#define XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA    0x110
+#define XV_CSC_CTRL_BITS_HWREG_GOFFSET_2_V_DATA    12
+#define XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA    0x118
+#define XV_CSC_CTRL_BITS_HWREG_BOFFSET_2_V_DATA    12
+#define XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA   0x120
+#define XV_CSC_CTRL_BITS_HWREG_CLAMPMIN_2_V_DATA   10
+#define XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA    0x128
+#define XV_CSC_CTRL_BITS_HWREG_CLIPMAX_2_V_DATA    10
--- a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.c
+++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.c
--- a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.h
+++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.h
@ -0,0 +1,397 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xv_csc_l2.h
+*
+* This header file contains layer 2 API's of the csc sub-core driver.
+* The functions contained herein provides a high level implementation of features
+* provided by the IP, abstracting away the register level details from
+* the user
+*
+* <b>Color Space Converter IP Features </b>
+*
+* The CSC IP supports following features
+*	- Set a Demo Window (user can select a sub-frame where above features
+*	  will have effect)
+*	- Supports resolution up to 4k2k 60Hz
+*	- up to 16 bits color depth
+*	- 1, 2 or 4 pixel per clock processing
+*
+* The Layer 2 driver of Color Space Conversion core offers following features
+*	- Set/Get Brightness, contrast, saturation
+*	- Set/Get Gain for R/G/B channel
+*	- Set/Get Input/Output Color Standard (BT601, BT709, BT2020)
+*	- Set/Get Input/Output Color Format (RGB, YUV444, YUV422)
+*	- All settings are translated between user range (0-100) and IP supported
+*	  range
+*
+* <b>Dependency</b>
+*
+* This driver makes use of the video enumerations and data types defined in the
+* Xilinx Video Common Driver (video_common_vX.x) and as such the common driver
+* must be included as dependency to compile this driver
+*
+* <b>Initialization & Configuration</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the CSC core.
+*
+* Before using the layer-2 API's user must initialize the core by calling
+* Layer-1 API XV_csc_Initialize(). This function will look for a configuration
+* structure for the device and initialize it to defined HW settings. After
+* initialization Layer-2 API's can be used to configure the core. It is
+* recommended user always make use of Layer-2 API to interact with the core
+* Advanced users always have the capability to directly interact with the
+* core using Layer-1 API's that perform low level register peek/poke.
+*
+* <b> Interrupts </b>
+*
+* This driver does not have any interrupts
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  rc   05/01/15   Initial Release
+
+* </pre>
+*
+******************************************************************************/
+#ifndef XV_CSC_L2_H            /* prevent circular inclusions */
+#define XV_CSC_L2_H            /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xvidc.h"
+#include "xv_csc.h"
+
+
+/****************************** Type Definitions ******************************/
+/**
+ * CSC Layer 2 Register Map. Each instance of the csc core will have it's own
+ * register map
+ */
+typedef enum
+{
+   CSC_FW_REG_ColStart = 0,
+   CSC_FW_REG_ColEnd,
+   CSC_FW_REG_RowStart,
+   CSC_FW_REG_RowEnd,
+   CSC_FW_REG_K11,
+   CSC_FW_REG_K12,
+   CSC_FW_REG_K13,
+   CSC_FW_REG_K21,
+   CSC_FW_REG_K22,
+   CSC_FW_REG_K23,
+   CSC_FW_REG_K31,
+   CSC_FW_REG_K32,
+   CSC_FW_REG_K33,
+   CSC_FW_REG_ROffset,
+   CSC_FW_REG_GOffset,
+   CSC_FW_REG_BOffset,
+   CSC_FW_REG_ClampMin,
+   CSC_FW_REG_ClipMax,
+   CSC_FW_REG_K11_2,
+   CSC_FW_REG_K12_2,
+   CSC_FW_REG_K13_2,
+   CSC_FW_REG_K21_2,
+   CSC_FW_REG_K22_2,
+   CSC_FW_REG_K23_2,
+   CSC_FW_REG_K31_2,
+   CSC_FW_REG_K32_2,
+   CSC_FW_REG_K33_2,
+   CSC_FW_REG_ROffset_2,
+   CSC_FW_REG_GOffset_2,
+   CSC_FW_REG_BOffset_2,
+   CSC_FW_REG_ClampMin_2,
+   CSC_FW_REG_ClipMax_2,
+   CSC_FW_NUM_REGS
+}XV_CSC_FW_REG_MMAP;
+
+/**
+ * This typedef contains the layer 2 register map for a given
+ * instance of the csc core.
+ */
+typedef struct
+{
+  XVidC_ColorFormat ColorFormatIn;
+  XVidC_ColorFormat ColorFormatOut;
+  XVidC_ColorStd StandardIn;
+  XVidC_ColorStd StandardOut;
+  XVidC_ColorRange OutputRange;
+  XVidC_ColorDepth ColorDepth;
+  s32 Brightness;
+  s32 Contrast;
+  s32 Saturation;
+  s32 RedGain;
+  s32 GreenGain;
+  s32 BlueGain;
+  s32 Brightness_active;
+  s32 Contrast_active;
+  s32 Saturation_active;
+  s32 RedGain_active;
+  s32 GreenGain_active;
+  s32 BlueGain_active;
+  s32 K_active[3][4];
+
+  s32 regMap[CSC_FW_NUM_REGS];
+}XV_csc_L2Reg;
+
+/************************** Macros Definitions *******************************/
+/*****************************************************************************/
+/**
+* This macro sets color depth for CSC core
+*
+* @param  pCscFwReg is a pointer to csc layer 2 fw register map
+* @param  val is the requested color depth
+*
+* @return None
+*
+******************************************************************************/
+#define XV_CscSetColorDepth(pCscFwReg, val)   ((pCscFwReg)->ColorDepth = val)
+
+/*****************************************************************************/
+/**
+* This macro returns current brightness setting by reading layer 2 fw register
+* map. It also translates between hw register value and user view
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return current user view value (0-100)
+*
+******************************************************************************/
+#define XV_CscGetBrightness(pCscFwReg)        (((pCscFwReg)->Brightness-20)/2)
+
+/*****************************************************************************/
+/**
+* This macro returns current contrast setting by reading layer 2 fw register
+* map. It also translates between hw register value and user view
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return current user view value (0-100)
+*
+******************************************************************************/
+#define XV_CscGetContrast(pCscFwReg)          (((pCscFwReg)->Contrast+200)/4)
+
+/*****************************************************************************/
+/**
+* This macro returns current saturation setting by reading layer 2 fw register
+* map. It also translates between hw register value and user view
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return current user view value (0-100)
+*
+******************************************************************************/
+#define XV_CscGetSaturation(pCscFwReg)        (((pCscFwReg)->Saturation/2))
+
+/*****************************************************************************/
+/**
+* This macro returns current red gain setting by reading layer 2 fw register
+* map. It also translates between hw register value and user view
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return current user view value (0-100)
+*
+******************************************************************************/
+#define XV_CscGetRedGain(pCscFwReg)           (((pCscFwReg)->RedGain-20)/2)
+
+/*****************************************************************************/
+/**
+* This macro returns current green gain setting by reading layer 2 fw register
+* map. It also translates between hw register value and user view
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return current user view value (0-100)
+*
+******************************************************************************/
+#define XV_CscGetGreenGain(pCscFwReg)         (((pCscFwReg)->GreenGain-20)/2)
+
+/*****************************************************************************/
+/**
+* This macro returns current blue gain setting by reading layer 2 fw register
+* map. It also translates between hw register value and user view
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return current user view value (0-100)
+*
+******************************************************************************/
+#define XV_CscGetBlueGain(pCscFwReg)          (((pCscFwReg)->BlueGain-20)/2)
+
+/*****************************************************************************/
+/**
+* This macro returns current set input color format by reading layer 2 fw
+* register map.
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return Current set input color format
+*		- XVIDC_CSF_RGB
+*		- XVIDC_CSF_YCRCB_444
+*		- XVIDC_CSF_YCRCB_422
+*
+******************************************************************************/
+#define XV_CscGetColorFormatIn(pCscFwReg)     ((pCscFwReg)->ColorFormatIn)
+
+/*****************************************************************************/
+/**
+* This macro returns current set output color format by reading layer 2 fw
+* register map.
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return Current set output color format
+*		- XVIDC_CSF_RGB
+*		- XVIDC_CSF_YCRCB_444
+*		- XVIDC_CSF_YCRCB_422
+*
+******************************************************************************/
+#define XV_CscGetColorFormatOut(pCscFwReg)    ((pCscFwReg)->ColorFormatOut)
+
+/*****************************************************************************/
+/**
+* This macro returns current set input color standard by reading layer 2 fw
+* register map.
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return Current set input color standard
+*		- XVIDC_BT_2020
+*		- XVIDC_BT_709
+*		- XVIDC_BT_601
+*
+******************************************************************************/
+#define XV_CscGetColorStdIn(pCscFwReg)        ((pCscFwReg)->StandardIn)
+
+/*****************************************************************************/
+/**
+* This macro returns current set output color standard by reading layer 2 fw
+* register map.
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return Current set output color standard
+*		- XVIDC_BT_2020
+*		- XVIDC_BT_709
+*		- XVIDC_BT_601
+*
+*****************************************************************************/
+#define XV_CscGetColorStdOut(pCscFwReg)       ((pCscFwReg)->StandardOut)
+
+/*****************************************************************************/
+/**
+* This macro returns current set output range by reading layer 2 fw register
+* map.
+*
+* @param  pCscFwReg is pointer to csc fw register associated with csc core
+*         instance
+*
+* @return Current set output range
+*		- XVIDC_CR_16_235
+*		- XVIDC_CR_16_240
+*		- XVIDC_CR_0_255
+*
+******************************************************************************/
+#define XV_CscGetOutputRange(pCscFwReg)       ((pCscFwReg)->OutputRange)
+
+/************************** Function Prototypes ******************************/
+void XV_CscStart(XV_csc *InstancePtr);
+void XV_CscStop(XV_csc *InstancePtr);
+void XV_CscSetActiveSize(XV_csc *InstancePtr,
+                         u32    width,
+                         u32    height);
+void XV_CscSetDemoWindow(XV_csc *InstancePtr, XVidC_VideoWindow *ActiveWindow);
+
+void XV_CscSetColorspace(XV_csc *InstancePtr,
+                         XV_csc_L2Reg  *pCscFwReg,
+                         XVidC_ColorFormat cfmtIn,
+                         XVidC_ColorFormat cfmtOut,
+                         XVidC_ColorStd    cstdIn,
+                         XVidC_ColorStd    cstdOut,
+                         XVidC_ColorRange  cRangeOut
+                         );
+
+void XV_CscInitPowerOnDefault(XV_csc_L2Reg *pCscFwReg);
+void XV_CscSetBrightness(XV_csc *InstancePtr,
+                         XV_csc_L2Reg *pCscFwReg,
+                         s32 val);
+void XV_CscSetContrast(XV_csc *InstancePtr,
+                        XV_csc_L2Reg *pCscFwReg,
+                        s32 val);
+void XV_CscSetSaturation(XV_csc *InstancePtr,
+                         XV_csc_L2Reg *pCscFwReg,
+                         s32 val);
+void XV_CscSetRedGain(XV_csc *InstancePtr,
+                      XV_csc_L2Reg *pCscFwReg,
+                      s32 val);
+void XV_CscSetGreenGain(XV_csc *InstancePtr,
+                        XV_csc_L2Reg *pCscFwReg,
+                        s32 val);
+void XV_CscSetBlueGain(XV_csc *InstancePtr,
+                       XV_csc_L2Reg *pCscFwReg,
+                       s32 val);
+void XV_CscDbgReportStatus(XV_csc *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_linux.c
+++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_linux.c
@ -0,0 +1,150 @@
+// ==============================================================
+// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+// Version: 2015.1
+// Copyright (C) 2015 Xilinx Inc. All rights reserved.
+//
+// ==============================================================
+
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xv_csc.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XV_csc_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XV_csc_uio_map maps[ MAX_UIO_MAPS ];
+} XV_csc_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XV_csc_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XV_csc_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XV_csc_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XV_csc_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XV_csc_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XV_csc_Initialize(XV_csc *InstancePtr, const char* InstanceName) {
+	XV_csc_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+	strcpy(file, "/sys/class/uio/");
+	strcat(file, namelist[i]->d_name);
+	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Ctrl' should be mapped to uioX/map0
+    InstancePtr->Ctrl_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Ctrl_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XV_csc_Release(XV_csc *InstancePtr) {
+	XV_csc_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Ctrl_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif
--- a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_sinit.c
+++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_sinit.c
@ -0,0 +1,45 @@
+// ==============================================================
+// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+// Version: 2015.1
+// Copyright (C) 2015 Xilinx Inc. All rights reserved.
+//
+// ==============================================================
+
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xv_csc.h"
+
+extern XV_csc_Config XV_csc_ConfigTable[];
+
+XV_csc_Config *XV_csc_LookupConfig(u16 DeviceId) {
+	XV_csc_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XV_CSC_NUM_INSTANCES; Index++) {
+		if (XV_csc_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XV_csc_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XV_csc_Initialize(XV_csc *InstancePtr, u16 DeviceId) {
+	XV_csc_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XV_csc_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XV_csc_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif