sw_services: Added support for CortexA9 to OpenAMP library
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
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516c7af2cb
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f75b62eb34
2 changed files with 11 additions and 8 deletions
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@ -46,8 +46,8 @@ proc openamp_drc {libhandle} {
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set hw_processor [common::get_property HW_INSTANCE $proc_instance]
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set hw_processor [common::get_property HW_INSTANCE $proc_instance]
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set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
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set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
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if { $proc_type != "psu_cortexr5" } {
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if { ( $proc_type != "psu_cortexr5" ) && ( $proc_type != "ps7_cortexa9" ) } {
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error "ERROR: This library is supported only for CortexR5 processors.";
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error "ERROR: This library is supported only for CortexR5 and CortexA9 processors.";
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return;
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return;
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}
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}
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}
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}
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@ -135,13 +135,16 @@ int remoteproc_resource_deinit(struct remote_proc *rproc) {
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env_deinit();
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env_deinit();
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/* Disable the caches - This is required if master boots firmwares
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/*
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* multiple times without hard reset on same core. If caches are
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* Flush and Invalidate the caches - When the application is built with
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* not invalidated at this point in time then subsequent firmware
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* Xilinx Standalone BSP, caches are invalidated as part of boot process.
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* boots on the same core may experience cache inconsistencies.
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* Even if the master boots firmware multiple times without hard reset on
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*
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* same core, caches are flushed and invalidated at the end of
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* remoteproc_resource_deinit for this run and caches would be again
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* invalidated before starting the main thread of the application on next
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* run to avoid any cache inconsistencies.
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*/
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*/
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env_disable_cache();
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platform_cache_all_flush_invalidate();
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return RPROC_SUCCESS;
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return RPROC_SUCCESS;
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}
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}
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