This patch fixes the issue AXI Ethernet with FIFO will fail to
create the BSP if the interrupt pin on the FIFO is unconnected.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
The axiethernet ip contains 3 inbuilt blocks init
--> Axi Ethernet MAC
--> Axi Etherent BUF
--> PCS/PMA Core
During the vivado version < 2015.2 the axiethernet ip
being exported to hdf in flat mode and the hsi opens this in flat mode.
But from 2015.3 build onwards the axiethernet ip is tagged as core in the vivado
and hsi will open the ip in hier IP mode(hierarchy) means for user only
top level axiethernet instance will be visible and it will contains all
the properties related to the sub-cores.
In order to allow backward compatabilty
---> If a xml/hdf file which got created with the vivado version < 2015.3 being exported to
the sdk >= 2015.3.
---> Two drivers will be active to resolve this issue.
---> axiethernet_v4_4 will be attached to BUF this will fix the backward compatabilty issue.
---> axiethernet_v5_0 will be attached to top level block for newer features.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
